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Service discovery strategies in ubiquitous communication environments

IEEE COMMUNICATIONS MAGAZINE 2006年第9期44卷 106-113页

作者： Sivavakeesar, Siva Gonzalez, Oscar F. Pavlou, George Univ Surrey Networks Res Grp Ctr Commun Syst Res Guildford GU2 5XH Surrey England

Past communication and computing trends are inadequate to deal with today's complex, distributed, and diverse network environments. With the recent development of small-size tetherless communication/computing devices and the increasing diversity in their capabilities, autonomic ubiquitous communication environments are emerging. In such environments, the execution of a complex task does not necessarily make use of prconfigured devices or networks, but requires instead the selection of suitable computing elements on-the-fly, based on the task requirements and device characteristics (i.e., networking-on-demand or task-centric networking). Research is currently being carried out in various dimensions in this emerging domain, including, among other approaches for context awareness, service discovery and self-management. In this article we concentrate on proposing a distributed mechanism for discovering suitable service elements on-the-fly.

关键词： UBIQUITOUS computing COMPUTER programming distributed computing EMBEDDED computer systems COMPUTER networks WIDE area networks (Computer networks) distributed shared memory COMPUTERS SYSTEMS development EMBEDDED computer systems -- Programming

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Benchmarking parallel compilers: A UPC case study

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2006年第7期22卷 764-775页

作者： El-Ghazawi, Tarek A. Cantonnet, Francois Yao, Yiyi Annareddy, Smita Mohamed, Ahmed S. George Washington Univ Dept Elect & Comp Engn Washington DC 20052 USA

Unified Parallel C (UPC) is an explicit parallel extension to ISO C which follows the Partitioned Global Address Space (PGAS) programming model. UPC, therefore, combines the ability to express parallelism while exploiting locality. To do so, compilers must embody effective UPC-specific optimizations. In this paper we present a strategy for evaluating the performance of PGAS compilers. It is based on emulating possible optimizations and comparing the performance to the raw compiler performance. It will be shown that this technique uncovers missed optimization opportunities. The results also demonstrate that, with such automatic optimizations, the UPC performance will be compared favorably with other paradigms. (C) 2006 Elsevier B.V. All rights reserved.

关键词： distributed shared memory unified parallel C compilers non-uniform memory accesses architecture benchmark NAS parallel benchmark

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Adapting workload distribution on software DSM clusters

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SOFTWARE-PRACTICE & EXPERIENCE 2006年第11-12期36卷 1133-1155页

作者： Liu, Yen-Tso Liang, Tyng-Yeu Shieh, Ce-Kuen Natl Kaohsiung Univ Appl Sci Dept Elect Engn Kaohsiung 807 Taiwan Natl Chung Kung Univ Dept Elect Engn Tainan 701 Taiwan

Achieving an appropriate workload distribution is essential if user applications are to achieve a satisfactory performance on software distributed shared memory (SDSM) clusters. To address this problem, the present study develops a novel method for distributing program threads onto the individual computers of SDSM clusters. In contrast to alternative methods, the proposed approach takes account not only of processor speed and data-sharing aspects, but also memory availability, such that application performance can be enhanced through the implementation of appropriate workload distributions. In addition, when distributing the program threads, the proposed method specifically chooses only those computers that can enhance the performance of the application, rather than simply distributing the threads to all the available nodes in the cluster. This location policy makes it possible to specify the appropriate node combinations that optimize program performance while simultaneously maximizing resource utilization. The proposed method is implemented on a testbed referred to as Teamster. The experimental results demonstrate that, compared to alternative methods, the proposed approach delivers a 20-30% improvement in the performance of the chosen test applications. Importantly, it is shown that the proposed method can efficiently specify proper node combinations for the applications. Copyright (C) 2006 John Wiley & Sons, Ltd.

关键词： distributed shared memory workload distribution memory availability location policy node combination

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A platform-independent distributed runtime for standard multithreaded java

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2006年第2期34卷 113-142页

作者： Factor, Michael Schuster, Assaf Shagin, Konstantin Technion Israel Inst Technol Dept Comp Sci IL-32000 Haifa Israel IBM Res Lab Haifa IL-31905 Haifa Israel

JavaSplit is a portable runtime environment for distributed execution of standard multithreaded Java programs. It gains augmented computational power and increased memory capacity by distributing the threads and objects of an application among the available machines. Unlike previous works, which either forfeit Java portability by using a nonstandard Java Virtual Machine (JVM) or compromise transparency by requiring user intervention in making the application suitable for distributed execution, JavaSplit automatically executes standard multithreaded Java on any heterogenous collection of Java-enabled machines. Each machine carries out its part of the computation using nothing but its local standard (unmodified) JVM. Neither the programmer nor the person submitting the program for execution needs to be aware of JavaSplit or its distributed nature. We evaluate the efficiency of JavaSplit on several combinations of operating systems, JVM implementations, and communication hardware.

关键词： distributed computing Java bytecode instrumentation distributed shared memory

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Refinement verification of the lazy caching algorithm

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ACTA INFORMATICA 2006年第3期43卷 195-222页

作者： Hesselink, Wim H. Univ Groningen Dept Math & Comp Sci NL-9700 AV Groningen Netherlands

The lazy caching algorithm of Afek et al. (ACM Trans. Program. Lang. Syst. 15, 182-206, 1993) is a protocol that allows the use of local caches with delayed updates. It results in a memory model that is not atomic (linearizable) but only sequentially consistent as defined by Lamport. In distributed Computing 12 (1999), specifying and proving sequential consistency for the lazy caching algorithm was made into a benchmark for verification models. The present note contains such a specification and proof. It provides a simulation from the implementation to the abstract specification. The concrete verification only relies on the state space and the next-state relation. All behavioural aspects are treated in theories independent of the specific algorithm. The proofs of the underlying theories and of the concrete algorithm have been verified with the proof assistant PVS.

关键词： distributed computing distributed shared memory FORMALISM (Art) ALGORITHMS BOOLEAN algebra

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Finding a suitable system scale to optimize program performance on software DSM systems

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CLUSTER COMPUTING-THE JOURNAL OF NETWORKS SOFTWARE TOOLS AND APPLICATIONS 2006年第3期9卷 223-236页

作者： Zhuang, Yi-Chang Chang, Jyh-Biau Liang, Ng-Yeu Shieh, Ce-Kuen Yang, Laurence Tianruo St Francis Xavier Univ Dept Comp Sci Antigonish NS B2G 2W5 Canada Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan Natl Kaohsiung Univ Appl Sci Dept Elect Engn Kaohsiung Taiwan

Recently, software distributed shared memory systems have successfully provided an easy user interface to parallel user applications on distributed systems. In order to prompt program performance, most of DSM systems usually were greedy to utilize all of available processors in a computer network to execute user programs. However, using more processors to execute programs cannot necessarily guarantee to obtain better program performance. The overhead of paralleling programs is increased by the addition in the number of processors used for program execution. If the performance gain from program parallel cannot compensate for the overhead, increasing the number of execution processors will result in performance degradation and resource waste. In this paper, we proposed a mechanism to dynamically find a suitable system scale to optimize performance for DSM applications according to run-time information. The experimental results show that the proposed mechanism can precisely predict the processor number that will result in the best performance and then effectively optimize the performance of the test applications by adapting system scale according to the predicted result.

关键词： distributed shared memory system scale program performance performance prediction

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A Practical Switch-memory-Switch Architecture Emulating PIFO OQ

A Practical Switch-Memory-Switch Architecture Emulating PIFO...

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IEEE Global Telecommunications Conference (GLOBECOM 06)

作者： Hua, Nan Xu, Yang Wang, Peng Jin, Depeng Zeng, Lieguang Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China Informat Engn Univ Zhengzhou 450002 Peoples R China

ISBN: (纸本)9781424403561

Emulating Output Queued (OQ) Switch with sustainable implementation cost and low fixed delay is always preferable in designing high performance routers. The Switch-memory-Switch (SMS) router, also called distributed shared memory (DSM) Switch, provides a possible way towards practically emulating OQ in backbone switches. However, the architectures and algorithms for SMS switches ever proposed are either unpractical or only supporting First-Come-First-Serve (FCFS) scheduling policy, which cannot support QoS and is unfair for light traffic flow. Our improved SMS architecture and algorithm aim at emulating Push-In-First-Out (PIFO) OQ. We employ a randomly-dispatching first stage and resolve memory access conflictions on the second stage of the switch through a probabilistic matching method, at the cost of fixed delay and sufficiently low cell loss probability (P-CLP). The relative fixed delay of our algorithms for an NxN switch is composed of two parts: N and (-3/2log(2)P(CLP)), which result from the pipelined scheduling process and probabilistic method, respectively. Moreover, both the total memory and fabric bandwidth of our architecture implemented on crossbar could be lowered to only 2NR, where R is line rate, counting read and write separately.

关键词： Switch-memory-Switch distributed shared memory Load-balanced Emulating PIFO OQ

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Reconfigurable interconnects in DSM systems: A focus on context switch behavior

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ISPA 2006 International Conference

作者： Artundo, I. Manjarres, D. Heirman, W. Debaes, C. Dambre, J. Van Campenhout, J. Thienpont, H. Vrije Univ Brussels Dept Appl Phys & Photon TONA Pleinlaan 2 B-1050 Brussels Belgium Genet Unit Elect & Informat Syst Dept B-9000 Ghent Belgium

ISBN: (纸本)9783540498605

Recent advances in the development of reconfigurable optical interconnect technologies allow for the fabrication of low cost and run-time adaptable interconnects in large distributed shared-memory (DSM) multiprocessor machines. This can allow the use of adaptable interconnection networks that alleviate the huge bottleneck present due to the gap between the processing speed and the memory access time over the network. In this paper we have studied the scheduling of tasks by the kernel of the operating system (OS) and its influence on communication between the processing nodes of the system, focusing on the traffic generated just after a context switch. We aim to use these results as a basis to propose a potential reconfiguration of the network that could provide a significant speedup.

关键词： reconfiguration interconnection network distributed shared memory multiprocessors context switch

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Lower level architecture of the Sombrero single address space distributed operating system

Lower level architecture of the Sombrero single address spac...

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18th IASTED International Conference on Parallel and distributed Computing and Systems

作者： Miller, Donald S. White, Donald B. Skousen, Alan C. Tcherepov, Rossen Arizona State Univ Dept Comp Sci & Engn Tempe AZ 85287 USA

ISBN: (纸本)9780889866386

Sombrero is an object-oriented single address space operating system whose virtual address space can be distributed over multiple nodes. This paper presents recent additions to the design and implementation of the lower level architecture of Sombrero. This design exploits Sombrero's object-oriented development model to provide an implementation of a lower-level architecture for the Alpha platform. Software representations of the hardware system's major components have been implemented. The existing middle level architectural modules now use the lower-level services, These include board and processor level hardware interfaces as well as interrupt processing, device driver and protocol component architectures. We contrast differences in the ways these things are designed and operate in a single address space environment with the way they are done in a conventional multiple address space operating system. Features covered include the use of passive servers, simple efficient thread switching and threads blocking within interrupts. Passive and active device drivers are described and the rational for each mode given. The performance of the Sombrero protocol stack was closely examined with attention to its passive service architecture and thread switching method. The current Sombrero Prototype is described.

关键词： single address space operating systems operating systems distributed operating systems object-oriented systems distributed shared memory

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Speeding up multiprocessor machines with reconfigurable optical interconnects

Speeding up multiprocessor machines with reconfigurable opti...

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Conference on Optoelectronic Integrated Circuits VIII

作者： Heirman, W. Artundo, I. Desmet, L. Dambre, J. Debaes, C. Thienpont, H. Van Campenhout, J. Univ Ghent ELIS Dept B-9000 Ghent Belgium Vrije Univ Brussel TONA Dept Brussels Belgium

ISBN: (纸本)0819461660

Electrical interconnection networks connecting the different processors and memory modules in modern large-scale multiprocessor machines are running into several physical limitations. In shared-memory machines, where the network is part of the memory hierarchy, high network latencies cause a significant performance bottleneck. Parallel optical interconnection technologies can alleviate this bottleneck by providing fast and high-bandwidth links. Moreover, new devices like tunable lasers and detectors or MEMS mirror arrays allow us to reconfigure the network at runtime in a data transparent way. This allows for extra connections between distant node pairs that communicate intensely, achieving a high virtual network connectivity by providing only a limited number of physical links at each moment in time. In this paper, we propose a reconfigurable network architecture that can be built using available low cost components and identify the limitations these components impose on network performance. We show, through detailed simulation of benchmark executions, that the proposed network can provide a significant speedup for shared-memory machines, even with the described limitations.

关键词： optical reconfiguration multiprocessor interconnection network distributed shared memory

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