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检索条件"主题词=distributed shared memory"

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A Bounded memory Allocator for Software-Defined Global Address Spaces 2016

A Bounded Memory Allocator for Software-Defined Global Addre...

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15th ACM SIGPLAN International Symposium on memory Management (ISMM 2016)

作者： Gindraud, Francois Rastello, Fabrice Cohen, Albert Broquedis, Francois UJF Grenoble France INRIA Paris France Grenoble INP Grenoble France

ISBN: (纸本)9781450343176

This paper presents a memory allocator targeting manycore architectures with distributed memory. Among the family of Multi Processor System on Chip (MPSoC), these devices are composed of multiple nodes linked by an on-chip network;most nodes have multiple processors sharing a small local memory. While MPSoC typically excel on their performance-per-Watt ratio, they remain hard to program due to multilevel parallelism, explicit resource and memory management, and hardware constraints (limited memory, network topology). Typical programming frameworks for MPSoC leave much target-specific work to the programmer: combining threads or node-local OpenMP, software caching, explicit message passing (and sometimes, routing), with non-standard interfaces. More abstract, automatic frameworks exist, but they target large-scale clusters and do not model the hardware constraints of MPSoC. The memory allocator described in this paper is one component of a larger runtime system, called Givy, to support dynamic task graphs with automatic software caching and data-driven execution on MPSoC. To simplify the programmer's view of memory, both runtime and program data objects live in a Global Address Space (GAS). To avoid address collisions when objects are dynamically allocated, and to manage virtual memory mappings across nodes, a GAS-aware memory allocator is required. This paper proposes such an allocator with the following properties: (1) it is free of inter-node synchronizations;(2) its node-local performance match that of state-of-the-art shared-memory allocators;(3) it provides node-local mechanisms to implement inter-node software caching within a GAS;(4) it is well suited for small memory systems (a few MB per node).

关键词： memory allocation global address space distributed shared memory

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Lower level architecture of the Sombrero single address space distributed operating system

Lower level architecture of the Sombrero single address spac...

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18th IASTED International Conference on Parallel and distributed Computing and Systems

作者： Miller, Donald S. White, Donald B. Skousen, Alan C. Tcherepov, Rossen Arizona State Univ Dept Comp Sci & Engn Tempe AZ 85287 USA

ISBN: (纸本)9780889866386

Sombrero is an object-oriented single address space operating system whose virtual address space can be distributed over multiple nodes. This paper presents recent additions to the design and implementation of the lower level architecture of Sombrero. This design exploits Sombrero's object-oriented development model to provide an implementation of a lower-level architecture for the Alpha platform. Software representations of the hardware system's major components have been implemented. The existing middle level architectural modules now use the lower-level services, These include board and processor level hardware interfaces as well as interrupt processing, device driver and protocol component architectures. We contrast differences in the ways these things are designed and operate in a single address space environment with the way they are done in a conventional multiple address space operating system. Features covered include the use of passive servers, simple efficient thread switching and threads blocking within interrupts. Passive and active device drivers are described and the rational for each mode given. The performance of the Sombrero protocol stack was closely examined with attention to its passive service architecture and thread switching method. The current Sombrero Prototype is described.

关键词： single address space operating systems operating systems distributed operating systems object-oriented systems distributed shared memory

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OPCAM: Optimal Algorithms Implementing Causal Memories in shared memory Systems 15

OPCAM: Optimal Algorithms Implementing Causal Memories in Sh...

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16th International Conference on distributed Computing and Networking

作者： Shen, Min Kshemkalyani, Ajay D. Hsu, Ta-yuan Univ Illinois Chicago IL 60607 USA

ISBN: (纸本)9781450329286

Data replication is commonly used for fault tolerance in reliable distributed systems. In this paper, we propose three optimal protocols for causal consistency in distributed shared memory systems. Our proposed optimal protocols are designed for partial replication across the distributed shared memory. Complete replication is a special case of our protocols and we also give the optimal implementation of causal consistency for the complete replication case. Algorithm Full-Track is optimal in the sense that it can update the local copy as soon as possible while respecting causal consistency. Algorithm Opt-Track is further optimal in the sense that the size of the local logs maintained and the amount of control information piggybacked on the update messages is minimal. Algorithm Opt-Track-CRP is a special case of algorithm Opt-Track for the full replication case. It is highly scalable, and significantly more efficient than the Baldoniet al. protocol for the complete replication case.

关键词： causal consistency distributed shared memory causality replication

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JCL: A High Performance Computing Java Middleware 18

JCL: A High Performance Computing Java Middleware

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18th International Conference on Enterprise Information Systems (ICEIS)

作者： Barroso Almeida, Andre Luis Delabrida Silva, Saul Emanuel Nazare, Antonio C., Jr. Lima, Joubert de Castro Univ Fed Ouro Preto DECOM Ouro Preto MG Brazil Univ Fed Ouro Preto CODAAUT Ouro Preto MG Brazil Univ Fed Minas Gerais DCC Belo Horizonte MG Brazil

ISBN: (纸本)9789897581878

Java Ca&La or just JCL is a distributed shared memory reflective lightweight middleware for Java developers whose main goals are: i) provide a simple deployment strategy, where automatic code registration occurs, ii) support a collaborative multi-developer cluster environment where applications can interact without explicit dependencies, iii) execute existing sequential Java code over both multi-core machines and cluster of multi-core machines without refactorings, enabling the separation of business logic from distribution issues in the development process, iv) provide a multi-core/ multi-computer portable code. This paper describes JCL's features and architecture;compares and contrasts JCL to other Java based middleware systems, and reports performance measurements of JCL applications.

关键词： Big Data Internet of Things Middleware Reflective Computing High Performance Computing distributed shared memory Remote Method Invocation

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Architectural Scheme for Future Embedded Systems involving large number of processing cores 7

Architectural Scheme for Future Embedded Systems involving l...

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7th International Conference on Cloud Computing, Data Science and Engineering (Confluence)

作者： Jafar, Sana Kumar, Pankaj Rajnish, Ranjana Jafar, Minsa Amity Univ Amity Sch Engn & Technol Lucknow Uttar Pradesh India Sri Ram Swaroop Coll Engn & Management Dept Comp Sci & Engn Lucknow Uttar Pradesh India Amity Univ Amity Inst Informat Technol Lucknow Uttar Pradesh India Jamia Hamdard Dept Comp Sci New Delhi India

ISBN: (纸本)9781509035199

Embedded system design is the core for many time constraint application designs like avionics and railways. These systems employ multi core architecture for faster and time critical applications. Use of mu Iti cores as the processing part is ever challenging due to the complexities involved in their designs, memory architecture, issues related to synchronization between the cores and problems like deadlock between the executing cores. Also as per the Moore's Law, number of cores on a single processing element increase exponentially becoming double after every 18 months. In the face of such fast increasing cores the time is not far when there will be 100 or 10 00's of cores on a single chip. Then there will be bigger challenges of dealing with problems like heat dissipation, concurrency control and speedy communication between the cores, without compromising the performance and outcome of embedded systems employing these multiple cores. In this paper we have studied some of the preexisting protocols and technologies for handling concurrency in large number of multi core systems and have proposed a framework for concurrency control with a routing protocol for multi core system employing 64 cores. Then we have proposed to stale this system for higher number of cores leading to up to 100 cores and will study the performance on an embedded system.

关键词： Embedded System multi care network top ology concurrency control distributed shared memory routing protocol

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An Interval Constrained memory Allocator for the Givy GAS Runtime 16

An Interval Constrained Memory Allocator for the Givy GAS Ru...

引用

21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Gindraud, Francoise Rastello, Fabrice Cohen, Albert Broquedis, Francoise UJF St Martin Dheres France Inria Rocquencourt France Grenoble INP Grenoble France

ISBN: (纸本)9781450340922

The shared memory model helps parallel programming productivity, but it also has a high hardware cost and imposes scalability constraints. Ultimately, higher performance will use distributed memories, which scales better but requires programmers to manually transfer data between local memories, which is a complex task. distributed memories are also more energy efficient than shared memories, and are used in a family of embedded computing solutions called multi processor system on chip (MPSoC).

关键词： memory allocation global address space distributed shared memory

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A DSM cluster architecture supporting aggressive computation in active networks

A DSM cluster architecture supporting aggressive computation...

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1st IEEE/AMC International Symposium on Cluster Computing and the Grid

作者： Graham, P Univ Manitoba Dept Comp Sci Parallel & Distributed Comp Lab Winnipeg MB R3T 2N2 Canada

ISBN: (纸本)0769510108;0769510116

Active networks allow computations to be performed in-network at routers as messages pass through them, Active networks offer unique opportunities to optimize network-centric applications in ways that are not possible using conventional networks. Unfortunately, the need to route packets at full network speed means that very little computation can be done per packet, per router This seriously restricts the range of in-network applications that can be developed. Computationally intensive applications are restricted to executing outside the network and thus many potential in-network optimizations are precluded. We propose a scalable cluster architecture using software distributed shared memory. (DSM) that can be used as an "attached processor" at routers for executing active code. This novel application of DSM enables the construction of aggressive active net-work protocols by providing significant compute capacity outside the router's critical packet routing path. The use of DSM simplifies the implementation, and extends the capabilities, of the active packet execution engine in ways that a message passing cluster cannot. Further, the characteristics of active processing enable specific optimizations to consistency maintenance.

关键词： active networks distributed shared memory cluster computing memory consistency

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Reliable Attributes Selection Technique for Predicting the Performance Measures of a DSM Multiprocessor Architecture

Reliable Attributes Selection Technique for Predicting the P...

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International Conference on Computer, Electrical and Electronics Engineering (ICCEEE)

作者： Zayid, Elrasheed Ismail Mohommoud Akay, Mehmet Fatih Univ Elimam Elmahdi Dept Comp Engn Kosti 11588 Sudan Cukurova Univ Dept Comp Engn Adana 01330 Turkey

ISBN: (纸本)9781467362313;9781467362320

In this study we develop a model for predicting the performance measures of a distributed shared memory (DSM) multiprocessor architecture by using a reliable attributes selection method. The structure of a DSM platform is interconnected by the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus), which is a low latency high bandwidth fiber-optic interconnection network. OPNET Modeler is used to simulate the SOME-Bus multiprocessor architecture and to create the datasets. The input variables chosen for the prediction model include the ratio service time over packet transfer time (varies from 0.01 to 1), traffic patterns (uniform, hot region, bit reverse and perfect shuffle), DSM protocol type, node number (varies to 16, 32 and 64), thread number (varies from 1 to 6). The attributes selection method examined the models using different machine learning tools. These tools include: multilayer feed forward artificial neural network (MFANNs), support vector regression with radial basis function (SVR-RBF) and multiple linear regression (MLR). Cross validation (CV) technique is applied using 10 folds. The results show that MFANN-based model gives the best results (i.e. SEE=11.1 and R = 0.998587 for CWT;SEE=18.96 and R = 0.997 for NRT;SEE=60.46 and R=0.8638 for IWT;SEE=0.04795 and R = 0.9838 for PU;SEE=0.0348 and R=0.9990 for CU). Results of the constructed new selected subset are compared with the original feature space and the findings prove the accuracy and reliability of the model.

关键词： distributed shared memory parallel multiprocessor architectures and artificial neural networks

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Speeding up multiprocessor machines with reconfigurable optical interconnects

Speeding up multiprocessor machines with reconfigurable opti...

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Conference on Optoelectronic Integrated Circuits VIII

作者： Heirman, W. Artundo, I. Desmet, L. Dambre, J. Debaes, C. Thienpont, H. Van Campenhout, J. Univ Ghent ELIS Dept B-9000 Ghent Belgium Vrije Univ Brussel TONA Dept Brussels Belgium

ISBN: (纸本)0819461660

Electrical interconnection networks connecting the different processors and memory modules in modern large-scale multiprocessor machines are running into several physical limitations. In shared-memory machines, where the network is part of the memory hierarchy, high network latencies cause a significant performance bottleneck. Parallel optical interconnection technologies can alleviate this bottleneck by providing fast and high-bandwidth links. Moreover, new devices like tunable lasers and detectors or MEMS mirror arrays allow us to reconfigure the network at runtime in a data transparent way. This allows for extra connections between distant node pairs that communicate intensely, achieving a high virtual network connectivity by providing only a limited number of physical links at each moment in time. In this paper, we propose a reconfigurable network architecture that can be built using available low cost components and identify the limitations these components impose on network performance. We show, through detailed simulation of benchmark executions, that the proposed network can provide a significant speedup for shared-memory machines, even with the described limitations.

关键词： optical reconfiguration multiprocessor interconnection network distributed shared memory

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Data Management Model to Program Irregular Compute Kernels on FPGA: Application to Heterogeneous distributed System 27th

Data Management Model to Program Irregular Compute Kernels o...

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27th International European Conference on Parallel and distributed Computing (Euro-Par)

作者： Lenormand, Erwan Goubier, Thierry Cudennec, Loic Charles, Henri-Pierre Univ Paris Saclay LIST CEA F-91191 Gif Sur Yvette France DGA Maitrise Informat BP 7 F-35998 Rennes France Univ Grenoble Alpes LIST CEA F-38000 Grenoble France

ISBN: (纸本)9783031061561;9783031061554

This paper presents a data management model targeting heterogeneous distributed systems integrating reconfigurable accelerators. The purpose of this model is to reduce the complexity of developing applications with multidimensional sparse data structures. It relies on a shared memory paradigm, which is convenient for parallel programming of irregular applications. The distributed data, sliced in chunks, are managed by a Software-distributed shared memory (S-DSM). The integration of reconfigurable accelerators in this S-DSM, by breaking the master-slave model, allows devices to initiate access to chunks in order to accept data-dependent accesses. We use chunk partitioning of multidimensional sparse data structures, such as sparse matrices and unstructured meshes, to access them as a continuous data stream. This model enables to regularize memory accesses of irregular applications, to avoid the transfer of unnecessary data by providing fine-grained data access, and to efficiently hide data access latencies by implicitly overlaying the transferred data flow with the processed data flow. We have used two case studies to validate the proposed data management model: General Sparse Matrix-Matrix Multiplication (SpGEMM) and Shallow Water Equations (SWE) over an unstructured mesh. The results obtained show that the proposed model efficiently hides the data access latencies by reaching computation speeds close to those of an ideal case (i.e. without latency).

关键词： distributed shared memory Field programmable gate array Irregular application

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