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丛书名： Synthesis lectures on computer architecture,

2013年

作者： Michael L. Scott

ISBN: (数字)9781608459575

ISBN: (纸本)9781608459568

Since the advent of time sharing in the 1960s, designers of concurrent and parallel systems have needed to synchronize the activities of threads of control that share data structures in memory. In recent years, the study of synchronization has gained new urgency with the proliferation of multicore processors, on which even relatively simple user-level programs must frequently run in parallel. This lecture offers a comprehensive survey of shared-memory synchronization, with an emphasis on "systems-level" issues. It includes sufficient coverage of architectural details to understand correctness and performance on modern multicore machines, and sufficient coverage of higher-level issues to understand how synchronization is embedded in modern programming languages. The primary intended audience is "systems programmers"—the authors of operating systems, library packages, language run-time systems, concurrent data structures, and server and utility programs. Much of the discussion should also be of interest to application programmers who want to make good use of the synchronization mechanisms available to them, and to computer architects who want to understand the ramifications of their design decisions on systems-level code. Table of Contents: Introduction / Architectural Background / Essential Theory / Practical Spin Locks / Busy-wait Synchronization with Conditions / Read-mostly Atomicity / Synchronization and Scheduling / Nonblocking Algorithms / Transactional memory / Author's Biography

关键词： distributed shared memory memory management (Computer science)

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Failure resilient real-time data federation system 09

Failure resilient real-time data federation system

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Proceedings of the 2009 Spring Simulation Multiconference

作者： Aakanksha Gagrani Brijesh Pillai Srikumar Krishnamoorthy Infosys Technologies Pvt. Ltd.

Data federation systems virtualize access to enterprize data resources by integrating data from disparate and heterogeneous operational data sources in an on-demand and real-time basis. The key challenge of low latency data access in such real-time data federation systems can be addressed by grid based scale-out architecture. However, failure of resources in the grid can pose serious challenges in data federation as the query processing is federated over multiple grid nodes. In such real-time data federation systems, it is often desirable to recover from failure and continue operation rather than repeat the entire process. This paper proposes a decentralized failure-recovery protocol for data federation system using data spaces based architecture. The generic nature of the protocol makes it extensible to applications other than data federation system as well. Moreover, the protocol does not make any assumptions about the availability of any central repository for recovering from failure. We implement the proposed failure recovery protocol in a simulation environment and present the key findings of the study.

关键词： failover grid computing distributed query processing distributed shared memory fault tolerance

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Interconnect Emulator for Aiding Performance Analysis of distributed memory Applications 16

Interconnect Emulator for Aiding Performance Analysis of Dis...

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Proceedings of the 7th ACM/SPEC on International Conference on Performance Engineering

作者： Qi Wang Ludmila Cherkasova Jun Li Haris Volos George Washington University Washington DC USA Hewlett Packard Labs Palo Alto USA

ISBN: (纸本)9781450340809

Many modern large graph and Big Data processing applications operate on datasets that do not fit into DRAM of a single machine. This leads to a design of scale-out applications, where the application dataset is partitioned and processed by a cluster of machines. distributed memory applications exhibit complex behavior: they tend to interleave computations and communications, use bursty transfers, and utilize global synchronization primitives. This makes it difficult to analyze the impact of communication layer on the application performance and answer the questions: how interconnect latency or bandwidth characteristics may change the application performance will the application performance scale when processed by a larger system? In this work, we introduce a novel emulation framework, called InterSense, which is implemented on top of existing high-speed interconnect, such as InfiniBand, and which provides two performance knobs for changing the (today's) interconnect bandwidth and latency. This approach offers an easy-to-use framework for a sensitivity analysis of complex distributed applications to communication layer performance instead of creating customized and time-consuming application models to answer the same questions. We evaluate the emulator accuracy with popular OSU MPI benchmark suite and two clusters with different generation InfiniBand interconnects (DDR and FDR): InterSense emulates the specified andwidth and latency values with less than 2% error between the expected and measured values. To demonstrate the InterSense's ease of use, we present a case study, where we apply InterSense for sensitivity analysis of four applications and benchmarks for getting non-trivial insights.

关键词： infiniband benchmarking performance emulation distributed shared memory MPI profiling

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Body area network for first responders: a case study 10

Body area network for first responders: a case study

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Proceedings of the Fifth International Conference on Body Area Networks

作者： Krzysztof Piotrowski Anna Sojka Peter Langendoerfer IHP Im Technologiepark Frankfurt (Oder) Germany

ISBN: (纸本)9781450300292

In this paper we present a case study for a design of a reliable body area network (BAN) for monitoring fire fighter rescue teams according to the requirements defined by the Berlin fire brigades. This case study considers all layers of the system, starting from the hardware, going through the operating system and data handling middleware, ending at the application layer. The main parts of the proposed solution are the tinyDSM middleware and a new prototyping hardware platform for wireless sensor nodes--IHPNode. The resulting BAN shall be a part of a larger system, where the BANs are connected via an additional multi-hop network to the control centre. Even if this connection fails, the BAN is able to take autonomous decisions. This system is developed within the FeuerWhere project.

关键词： distributed computing wireless sensor networks distributed shared memory

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View-Based Consistency and Its Implementation 01

View-Based Consistency and Its Implementation

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Proceedings of the 1st International Symposium on Cluster Computing and the Grid

作者： Z. Huang S. Cranefield M. Purvis C. Sun

ISBN: (纸本)9780769510101

This paper proposes a novel View-based Consistency model for distributed shared memory. A view is a set of ordinary data objects that a processor has the right to access in a data-race-free program. The View-based Consistency model only requires that the data objects of a view are updated before a processor accesses them. Compared with other memory consistency models, the View-based Consistency model can achieve data selection without user annotation and can reduce much false-sharing effect. This model has been implemented based on TreadMarks. Performance results have shown that for all our applications the View-based Consistency model outperforms the Lazy Release Consistency model.

关键词： False Sharing. Sequential Consistency distributed shared memory

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A distributed hypervisor for resource aggregation: poster 19

A distributed hypervisor for resource aggregation: poster

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Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming

作者： Yubin Chen Zhuocheng Ding Jin Zhang Yun Wang Zhengwei Qi Haibing Guan Shanghai Jiao Tong University

ISBN: (纸本)9781450362252

Scale-out has become the standard answer to data analysis, machine learning and many other fields. Contrary to common belief, scale-up machines can outperform scale-out clusters for a considerable portion of tasks. However, those scale-up machines are not economical and may not be affordable for small businesses. This paper presents GiantVM, a distributed hypervisor that aggregates resources from multiple physical machines, providing the guest OS with a uniform hardware abstraction. We propose techniques to deal with the challenges of CPU, memory, and I/O virtualization in distributed environments.

关键词： distributed shared memory

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Enabling shared memory communication in networks of MPSoCs

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2019年第21期31卷

作者： Lant, Joshua Concatto, Caroline Attwood, Andrew Pascual, Jose A. Ashworth, Mike Navaridas, Javier Lujan, Mikel Goodacre, John Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

Ongoing transistor scaling and the growing complexity of embedded system designs has led to the rise of MPSoCs (Multi-Processor System-on-Chip), combining multiple hard-core CPUs and accelerators (FPGA, GPU) on the same physical die. These devices are of great interest to the supercomputing community, who are increasingly reliant on heterogeneity to achieve power and performance goals in these closing stages of the race to exascale. In this paper, we present a network interface architecture and networking infrastructure, designed to sit inside the FPGA fabric of a cutting-edge MPSoC device, enabling networks of these devices to communicate within both a distributed and shared memory context, with reduced need for costly software networking system calls. We will present our implementation and prototype system and discuss the main design decisions relevant to the use of the Xilinx Zynq Ultrascale+, a state-of-the-art MPSoC, and the challenges to be overcome given the device's limitations and constraints. We demonstrate the working prototype system connecting two MPSoCs, with communication between processor and remote memory region and accelerator. We then discuss the limitations of the current implementation and highlight areas of improvement to make this solution production-ready.

关键词： distributed shared memory FPGA HPC interconnect MPSoC networks

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Integrating coordinated checkpointing and recovery mechanisms into DSM synchronization barriers

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ACM Journal of Experimental Algorithmics 2006年 11卷 2.9–es页

作者： Boukerche, Azzedine De Melo, Alba Cristina Magalhaes Alves School of Information Technology and Engineering University of Ottawa Canada Department of Computer Science University of Brasilia Brasilia Brazil

distributed shared memory (DSM) creates an abstraction of a physical shared memory that parallel programmers can access. Most recent software DSM systems provide relaxed-memory models that guarantee consistency only at synchronization operations, such as locks and barriers. As the main goal of DSM systems is to provide support for long-term computation-intensive applications, checkpointing and recovery mechanisms are highly desirable. This article presents and evaluates the integration of a coordinated checkpointing mechanism to the barrier primitive that is usually provided with many DSM systems. Our results on some popular benchmarks and a real parallel application show that the overhead introduced during the failure-free execution is often small. © 2006 ACM.

关键词： Algorithms Barrier synchronization D.1.3 [Concurrent Programming]-Parallel Programming D.4.5 [Reliability]-Checkpoint/restart, fault tolerance Design distributed shared memory Performance Reliability

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A Homogeneous Many-core x86 Processor Full System Framework Based on NoC

A Homogeneous Many-core x86 Processor Full System Framework ...

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International Conference on Computer Science and Network Technology

作者： Qinhong Zhang Meng Zhou Juan Chen Hao Yang The 28th Research Institute of China Electronics Technology Group Corporation Nanjing China Institute of Microelectronics Tsinghua University Beijing China

ISBN: (纸本)9781467381741

With the development of processor technique, more and more processor cores are integrated in a single chip to achieve higher performance requirements. Network-on-Chip (NoC) is the substitute for bus interconnection on many-core processor framework. In this paper, we propose a NoC based homogeneous many-core x86 processor architecture with distributed shared memory and high speed Network Interface (NI). By integrating the GEMS computer system simulator and the Booksim NoC simulator, we design a many-core x86 processor full system framework The experiment result of PARSEC benchmark shows that the framework is working efficiently with high performance.

关键词： many-core processor full system framework Network-on-Chip network-on-chip PROCESSOR NOCT gene quad-issue processor Multi-core processors Frameworks distributed shared memory

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Device Driver Programming in a Transactional DSM Operating System 02

Device Driver Programming in a Transactional DSM Operating S...

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Asia-Pacific Computer Systems Architecture Conference

作者： T. Bindhammer R. Goeckelmann O. Marquardt M. Schoettner M. Wende P. Schuithess Department of Distributed Systems University Ulm Oberer Eselsberg 27 89069 Ulm

ISBN: (纸本)0909925844

The Plurix project implements an object-oriented operating system (OS) for PC clusters. Network communication is implemented via the distributed shared memory (DSM) paradigm. memory consistency is maintained by restartable transactions and an optimistic synchronization scheme, that have been used in database technology in the past. Originally, DSM systems were built to support parallel algorithms, but using DSM as a foundation for a general purpose OS offers interesting perspectives in designing and using distributed applications. The OS, including kernel and all drivers, is written in Plurix Java. Our Java compiler directly translates Java source code into Intel machine instructions. Some minor language extensions support device-level programming. During the development of the system we identified conceptual problems which are caused by the restartability requirement of transactions. Clearly interrupts do not reoccur in case of an aborted transaction. Without proper precaution interrupts would get lost or devices could receive broken commands. In this paper we shortly review our DSM system and present the "smart buffer" concept to bridge the gap between restartable DSM transactions and non-restartable device operations and events. Finally, we validate our proposed solution by performance measurements and compare the kernel interface to traditional operating systems.

关键词： distributed shared memory driver development optimistic concurrency control operating system Operating systems distributed shared memory Concurrency control Java compiler Java source code Network communication device drivers

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