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RAPID: Reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors

JOURNAL OF LIGHTWAVE TECHNOLOGY 2004年第9期22卷 2101-2110页

作者： Kodi, AK Louri, A Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

In this paper, we describe the design and analysis of a scalable architecture suitable for large-scale distributed shared memory (DSM) systems. The approach is based on an interconnect technology which combines optical components and a novel architecture design. In DSM systems, numerous shared memory transactions such as requests, responses and acknowledgment messages propagate simultaneously in the network. As the network size increases, network contention results in increasing the critical remote memory access latency, which significantly penalizes the performance of DSM systems. In our proposed architecture called reconfigurable and scalable all-photonic interconnect for distributed-shared memory (RAPID), we provide high connectivity by maximizing the channel availability for remote communication to reduce the critical remote latency. RAPID provides fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed wavelength division multiplexing (WDM), time division multiplexing (TDM), and space division multiplexing (SDM) techniques. RAPID is wavelength-routed, permitting the same limited set of wavelength to be reused among all processors., We evaluated RAPID based on network characteristics, power budget criteria, and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh, and hypercube networks. We found that RAPID outperforms all networks and still provides good performance as the network is scaled to very large numbers.

关键词： cache coherence distributed shared memory optical interconnects scalable optical networks

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Performance improvement of parallel programs on a broadcast-based distributed shared memory multiprocessor by simulation

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SIMULATION MODELLING PRACTICE AND THEORY 2008年第3期16卷 338-352页

作者： Akay, Mehmet Fatih Katsinis, Constantine Cukurova Univ TR-01330 Adana Turkey Drexel Univ Coll Evening Studies Philadelphia PA 19104 USA

Due to advances in fiber optics and VLSI technology, interconnection networks that allow simultaneous broadcasts are becoming feasible. distributed shared memory (DSM) implementations on such networks promise high performance even for small applications with small granularity. This paper, after summarizing the architecture of one such implementation called the Simultaneous Multiprocessor Optical Exchange Bus (SOME-Bus), presents simple algorithms for improving the performance of parallel programs running on the SOME-Bus multiprocessor implementing cache-coherent DSM. The algorithms are based on run-time data redistribution via dynamic page migration protocol. They use memory access references together with the information of average channel utilization, average channel waiting time, number of messages in the channel queue or short-term average channel waiting time reported by each node and gathered by hardware monitors to make correct decisions related to the placement of shared data. Simulations with four parallel codes on a 64-processor SOME-Bus show that the algorithms yield significant performance improvements such as reduction in the execution times, number of remote memory accesses, average channel waiting times, average network latencies and increase in average channel utilizations. (C) 2007 Elsevier B.V. All rights reserved.

关键词： distributed shared memory multiprocessors interconnection networks

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A quantitative analysis of the performance and scalability of distributed shared memory cache coherence protocols

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IEEE TRANSACTIONS ON COMPUTERS 1999年第2期48卷 205-217页

作者： Heinrich, M Soundararajan, V Hennessy, J Gupta, A Cornell Univ Sch Elect Engn Ithaca NY 14853 USA Stanford Univ Comp Syst Lab Stanford CA 94305 USA Microsoft Corp Res Redmond WA 98052 USA

Scalable cache coherence protocols have become the key technology for creating moderate to large-scale shared-memory multiprocessors. Although the performance of such multiprocessors depends critically on the performance of the cache coherence protocol, little comparative performance data is available. Existing commercial implementations use a variety of different protocols, including bit-vector/coarse-vector protocols, SCI-based protocols, and COMA protocols. Using the programmable protocol processor of the Stanford FLASH multiprocessor, we provide a detailed, implementation-oriented evaluation of four popular cache coherence protocols. In addition to measurements of the characteristics of protocol execution (e.g., memory overhead, protocol execution time, and message count) and of overall performance, we examine the effects of scaling the processor count from 1 to 128 processors. Surprisingly, the optimal protocol changes for different applications and can change with processor count even within the same application. These results help identify the strengths of specific protocols and illustrate the benefits of providing flexibility in the choice of cache coherence protocol.

关键词： cache coherence protocols distributed shared memory FLASH MAGIC performance comparison scalable multiprocessors flexible node controller bitvector SCI COMA dynamic pointer allocation controller occupancy

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Cache-coherent distributed shared memory: Perspectives on its development and future challenges

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PROCEEDINGS OF THE IEEE 1999年第3期87卷 418-429页

作者： Hennessy, J Heinrich, M Gupta, A Stanford Univ Comp Syst Lab Stanford CA 94305 USA Cornell Univ Sch Elect Engn Ithaca NY 14853 USA Microsoft Inc Microsoft Res Redmond WA 98052 USA

distributed shared memory is an architectural approach that allows multiprocessors to support a single shared address space that is implemented with physically distributed memories. Hardware-supported distributed shared memory is becoming the dominant approach for building multiprocessors with moderate to large numbers of processors. Cache coherence allows such architectures to use caching to take advantage of locality in applications without changing the programmer's model of memory. We review the key developments that led to the creation of cache-coherent distributed shared memory and describe the Stanford DASH multiprocessor, the first working implementation of hardware-supported scalable cache coherence. We then provide a perspective on such architectures and discuss important remaining technical challenges.

关键词： cache coherence directory-based cache coherence distributed shared memory multiprocessor architecture scalable multiprocessors

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An asynchronous protocol for release consistent distributed shared memory systems

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JOURNAL OF SUPERCOMPUTING 2003年第1期24卷 25-41页

作者： Yeo, JH Yeom, HY Park, T Seoul Natl Univ Dept Comp Sci Seoul 151742 South Korea Sejong Univ Dept Comp Engn Seoul 143747 South Korea

distributed shared memory (DSM) systems provide a simple programming paradigm for networks of workstations, which are gaining popularity due to their cost-effective high computing power. However, DSM systems usually exhibit poor performance due to the large communication delay between the nodes;and a lot of different memory consistency models have been proposed to mask the network delay. In this paper, we propose an asynchronous protocol for the release consistent memory model, which we call an Asynchronous Release Consistency ( ARC) protocol. Unlike other protocols where the communication adheres to the synchronous request/receive paradigm, the ARC protocol is asynchronous, such that the necessary pages are broadcast before they are requested. Hence, the network delay can be reduced by proper prefetching of necessary pages. We have also compared the performance of the ARC protocol with the lazy release protocol by running standard benchmark programs;and the experimental results showed that the ARC protocol achieves a performance improvement of up to 29%.

关键词： distributed shared memory lazy release consistency asynchronous release consistency page fault

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Adaptive protocols for software distributed shared memory

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PROCEEDINGS OF THE IEEE 1999年第3期87卷 467-475页

作者： Amza, C Cox, AL Dwarkadas, S Jin, LJ Rajamani, K Zwaenepoel, W Rice Univ Dept Comp Sci Houston TX 77005 USA Univ Rochester Dept Comp Sci Rochester NY 14627 USA Univ Virginia Dept Comp Sci Charlottesville VA 22901 USA

We demonstrate the benefits of software shared memory protocols that adapt at run time to the memory access patterns observed in the applications. This adaptation is automatic-no user annotations cri-e required-and does not rely on compiler support or special hardware. We investigate adaptation between single- and multiple-writer protocols, dynamic aggregation of pages into a larger transfer unit, and adaptation between invalidate and update. Our results indicate that adaptation between single- and multiple-writer and dynamic aggregation are clearly beneficial. The results for the adaptation between invalidate and update are less compelling, showing at best gains similar to the dynamic aggregation adaptation cold at worst serious performance deterioration.

关键词： adaptive protocols application access patterns automatic adaptation distributed shared memory dynamic aggregation migratory access pattern single-writer versus multiple writer

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Predicting the performance measures of an optical distributed shared memory multiprocessor by using support vector regression

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EXPERT SYSTEMS WITH APPLICATIONS 2010年第9期37卷 6293-6301页

作者： Akay, M. Fatih Abasikeles, Ipek Cukurova Univ Dept Comp Engn Adana Turkey

Recent advances in the development of optical technologies suggest the possible emergence of optical interconnects within distributed shared memory (DSM) multiprocessors. The performance of these DSM architectures must be evaluated under varying values of DSM parameters. In this paper, we develop a Support Vector Regression (SVR) model for predicting the performance measures (i.e. average network latency, average channel waiting time and average processor utilization) of a DSM multiprocessor architecture interconnected by the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus), which is a high-bandwidth, fiber-optic interconnection network. The basic idea is to collect a small number of data points by using a statistical simulation and predict the performance measures of the system for a large set of input parameters based on these. OPNET Modeler is used to simulate the DSM-based SOME-Bus multiprocessor architecture and to create the training and testing datasets. The prediction error and correlation coefficient of the SVR model is compared to that of Multiple Linear Regression (MLR) and feedforward Artificial Neural Network (ANN) models. Results show that the SVR-RBF model has the lowest prediction error and is more robust. It is concluded that SVR model shortens the time quite a bit for obtaining the performance measures of a DSM multiprocessor and can be used as an effective tool for this purpose. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： Support vector regression Multiprocessors distributed shared memory Interconnection networks

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Scalability Analysis of memory Consistency Models in NoC-based distributed shared memory SoCs

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2013年第5期32卷 760-773页

作者： Naeem, Abdul Jantsch, Axel Lu, Zhonghai KTH Royal Inst Technol Dept Elect Syst Sch Informat & Commun Technol SE-16440 Stockholm Sweden

We analyze the scalability of six memory consistency models in network-on-chip (NoC)-based distributed shared memory multicore systems: 1) protected release consistency (PRC);2) release consistency (RC);3) weak consistency (WC);4) partial store ordering (PSO);5) total store ordering (TSO);and 6) sequential consistency (SC). Their realizations are based on a transaction counter and an address-stack-based approach. The scalability analysis is based on different workloads mapped on various sizes of networks using different problem sizes. For the experiments, we use Nostrum NoC-based configurable multicore platform with a 2-D mesh topology and a deflection routing algorithm. Under the synthetic workloads, the average execution time for the PRC, RC, WC, PSO, and TSO models in the 8 x 8 network (64-cores) is reduced by 32.3%, 28.3%, 20.1%, 13.8%, and 9.9% over the SC model, respectively. For the application workloads, as the network size grows, the average execution time under these relaxed memory models decreases with respect to the SC model depending on the application and its match to the architecture. The performance improvement of the PRC and RC models over the SC model tends to be higher than 50% as observed in the experiments, when the system is further scaled up. The area cost in the network interface for the relaxed memory models is increased by less than 4% over the SC model.

关键词： distributed shared memory memory consistency network-on-chip performance scalability

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Delay tolerant lazy release consistency for distributed shared memory in opportunistic networks

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PERVASIVE AND MOBILE COMPUTING 2016年 29卷 57-72页

作者： Eary, Chance Kumar, Mohan Zaruba, Gergely Univ Texas Arlington Dept Comp Sci & Engn Box 19015500 UTA BlvdRoom ERB 559 Arlington TX 76019 USA Rochester Inst Technol Dept Comp Sci 102 Lomb Mem Dr Rochester NY 14623 USA

Opportunistic networks (ONs) allow mobile wireless devices to interact with one another through a series of opportunistic contacts. While ONs exploit mobility of devices to route messages and distribute information, the intermittent connections among devices make many traditional computer collaboration paradigms, such as distributed shared memory (DSM), very difficult to realize. DSM systems, developed for traditional networks, rely on relatively stable, consistent connections among participating nodes to function properly. We propose a novel delay tolerant lazy release consistency (DTLRC) mechanism for implementing distributed shared memory in opportunistic networks. DTLRC permits mobile devices to remain independently productive while separated, and provides a mechanism for nodes to regain coherence of shared memory if and when they meet again. DTLRC allows applications to utilize the most coherent data available, even in the challenged environments typical to opportunistic networks. Simulations demonstrate that DTLRC is a viable concept for enhancing cooperation among mobile wireless devices in opportunistic networking environment. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Opportunistic networks Delay tolerant networks distributed systems distributed shared memory Lazy release consistency

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LUC Model : A Timestamp Ordering based View Consistency Model for distributed shared memory

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JOURNAL OF COMPUTERS 2010年第12期5卷 1828-1838页

作者： Rafat, Rubaiyat Islam Sakib, Kazi Univ Dhaka Inst Informat Technol Informat Technol Dhaka Bangladesh Univ Dhaka Inst Informat Technol Dhaka Bangladesh

Excessive locking and cumulative updates in distributed shared memory (DSM) not only reduces the parallelism for block access but also causes a serious degradation in response time for a dense network. This paper proposes a new consistency model in DSM named Last Update Consistency (LUC) model, where the model uses logical clock counter to keep the DSM consistent. The logical clock always increases never decreases. So the increasing order of the logical clock value is used to provide the request to the DSM. In this model, multiple nodes can perform READ operations over the same block at a time. For WRITE operation over the same block, only the last modification will exist and the earlier WRITE operations will be treated as obsolete WRITE and should be discarded. The experimental and analytical analysis showed that the proposed model effectively reduces the unnecessary network traffic and cumulative block updates that exist in the Sequential Consistency Model and Release Consistency Model.

关键词： View Consistency Model Timestamp Ordering Protocol distributed shared memory

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