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Enabling shared memory communication in networks of MPSoCs

CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2019年第21期31卷

作者： Lant, Joshua Concatto, Caroline Attwood, Andrew Pascual, Jose A. Ashworth, Mike Navaridas, Javier Lujan, Mikel Goodacre, John Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

Ongoing transistor scaling and the growing complexity of embedded system designs has led to the rise of MPSoCs (Multi-Processor System-on-Chip), combining multiple hard-core CPUs and accelerators (FPGA, GPU) on the same physical die. These devices are of great interest to the supercomputing community, who are increasingly reliant on heterogeneity to achieve power and performance goals in these closing stages of the race to exascale. In this paper, we present a network interface architecture and networking infrastructure, designed to sit inside the FPGA fabric of a cutting-edge MPSoC device, enabling networks of these devices to communicate within both a distributed and shared memory context, with reduced need for costly software networking system calls. We will present our implementation and prototype system and discuss the main design decisions relevant to the use of the Xilinx Zynq Ultrascale+, a state-of-the-art MPSoC, and the challenges to be overcome given the device's limitations and constraints. We demonstrate the working prototype system connecting two MPSoCs, with communication between processor and remote memory region and accelerator. We then discuss the limitations of the current implementation and highlight areas of improvement to make this solution production-ready.

关键词： distributed shared memory FPGA HPC interconnect MPSoC networks

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An Improved Algorithm about Failure Agreement based on distributed shared memory

An Improved Algorithm about Failure Agreement based on Distr...

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International Conference on Advanced in Control Engineering and Information Science (CEIS)

作者： Wang, Jun Jiang, Yaqiong Guilin Univ Elect Technol Financial Dept Guilin Peoples R China Guilin Univ Elect Technol Network Informat Ctr Guilin Peoples R China

According to the uniform addressing and direct localization of network address space, adopting multi-threaded, multi-copy store and block storage in pages, page tree sub-node parallel failure methods, these can improve the efficiency and parallel processing of the DSM system. It is significance for improving the performance of distributed systems. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [CEIS 2011]

关键词： distributed shared memory Failure Agreement Algorithm Security Parallelism

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Is It Time To Rethink distributed shared memory Systems?

Is It Time To Rethink Distributed Shared Memory Systems?

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17th IEEE International Conference on Parallel and distributed Systems (ICPADS)

作者： Ramesh, Bharath Ribbens, Calvin J. Varadarajan, Srinidhi Virginia Tech Ctr High End Comp Syst Dept Comp Sci Blacksburg VA 24061 USA

ISBN: (纸本)9780769545769

We present core elements of Samhita, a new user-level software distributed shared memory (DSM) system. Our work is motivated by two observations. First, the rise of many-core architectures is producing a growing emphasis on threaded codes to achieve performance. Second, architectural trends, especially in high performance interconnects, suggest a new look at overcoming the bottlenecks that have hindered DSM performance. Samhita leverages the capabilities of remote direct memory access (RDMA) interconnects, and views the problem of providing a shared global address space as a cache management problem. Performance results on two 256 processor clusters demonstrate scalability on microbenchmarks and two real applications. The results are the largest scale tests and achieve the highest performance of any DSM system reported to date.

关键词： distributed shared memory distributed run-time systems distributed systems

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Trusted Performance Analysis on Systems With a shared memory

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IEEE SYSTEMS JOURNAL 2017年第1期11卷 272-282页

作者： Zhao, Jiaqi Xue, Changlong Tao, Jie Ranjan, Rajiv Kolodziej, Joanna Wang, Lizhe Chen, Dan Changchun Univ Technol Sch Basic Sci Changchun 130012 Peoples R China Jilin Prov High Class Highway Construct Bur Changchun 130033 Peoples R China Karlsruhe Inst Technol Steinbuch Ctr Comp D-76021 Karlsruhe Germany Commonwealth Sci & Ind Res Org ICT Ctr Canberra ACT 2601 Australia Cracow Univ Technol Inst Comp Sci PL-31155 Krakow Poland AGH Univ Sci & Technol Intelligent Informat Syst Grp PL-30059 Krakow Poland Chinese Acad Sci Inst Remote Sensing & Digital Earth Beijing 100094 Peoples R China China Univ Geosci Sch Comp Sci Beijing 100083 Peoples R China Wuhan Univ Sch Comp Sci Wuhan 430072 Peoples R China

With the increasing complexity of both data structures and computer architectures, the performance of applications needs fine tuning in order to achieve the expected runtime execution time. Performance tuning is traditionally based on the analysis of performance data. The analysis results may not be accurate, depending on the quality of the data and the applied analysis approaches. Therefore, application developers may ask: Can we trust the analysis results? This paper introduces our research work in performance optimization of the memory system, with a focus on the cache locality of a shared memory and the memory locality of a distributed shared memory. The quality of the data analysis is guaranteed by using both real performance data acquired at the runtime while the application is running and well-established data analysis algorithms in the field of bioinformatics and data mining. We verified the quality of the proposed approaches by optimizing a set of benchmark applications. The experimental results show a significant performance gain.

关键词： Code optimization data analysis data locality distributed shared memory performance tuning

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The AXIOM platform for next-generation cyber physical systems

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MICROPROCESSORS AND MICROSYSTEMS 2017年 52卷 540-555页

作者： Theodoropoulos, Dimitris Mazumdar, Somnath Ayguade, Eduard Bettin, Nicola Bueno, Javier Ermini, Sara Filgueras, Antonio Jimenez-Gonzalez, Daniel Alvarez Martinez, Carlos Martorell, Xavier Montefoschi, Francesco Oro, David Pnevmatikatos, Dionisis Rizzo, Antonio Gai, Paolo Garzarella, Stefano Morelli, Bruno Pomella, Alberto Giorgi, Roberto Fdn Res & Technol Hellas FORTH Inst Comp Sci Iraklion Greece Univ Siena Dipartimento Ingn Informaz & Sci Matemat Siena Italy BSC Barcelona Spain VIMAR SpA Marostica Marostica Italy Univ Siena Dipartimento Sci Sociali Polit & Cognit Siena Italy Univ Politecn Cataluna Comp Architecture Dept Barcelona Spain Herta Secur Barcelona Barcelona Spain Tech Univ Crete Sch ECE Khania Greece Evidence Srl San Giuliano Terme Italy

Cyber-Physical Systems (CPSs) are widely used in many applications that require interactions between humans and their physical environment. These systems usually integrate a set of hardware-software components for optimal application execution in terms of performance and energy consumption. The AXIOM project (Agile, eXtensible, fast I/O Module), presented in this paper, proposes a hardware-software platform for CPS coupled with an easy parallel programming model and sufficient connectivity so that the performance can scale-up by adding multiple boards. AXIOM supports a task-based programming model based on OmpSs and leverages a high-speed, inexpensive communication interface called AXIOM-Link. The board also tightly couples the CPU with reconfigurable resources to accelerate portions of the applications. As case studies, AXIOM uses smart video surveillance, and smart home living applications. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Cyber-physical systems distributed shared memory Programming model Performance evaluation Reconfigurable Smart video surveillance Smart home living

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Minimizing Context Migration in Mobile Code Offload

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IEEE TRANSACTIONS ON MOBILE COMPUTING 2017年第4期16卷 1005-1018页

作者： Li, Yong Gao, Wei Univ Tennessee Dept Elect & Comp Sci 1520 Middle Dr Knoxville TN 37996 USA

Mobile Cloud Computing (MCC) is of particular importance to address the conflict between the increasing complexity of user applications and the limited lifespan of mobile device's battery, by offloading the computational workloads from local devices to the remote cloud. Current offloading schemes either require the programmer's annotations, which restricts its wide application;or transmits too much unnecessary data, resulting bandwidth, and energy waste. In this paper, we propose a novel method-level offloading methodology to offload local computational workload with as least data transmission as possible. Our basic idea is to identify the contexts which are necessary to the method execution by parsing application binaries in advance and applying this parsing result to selectively migrate heap data while allowing successful method execution remotely. To further improve the efficiency of such offline parsing of application binaries, our scheme also conducts one-time parsing to all the mobile OS libraries and reuses these parsing results for different user applications. We have implemented our design over the Dalvik Virtual Machine of Android OS. Our experiments and evaluation against applications downloaded from Google Play show that our approach can save data transmission significantly comparing to existing schemes.

关键词： Mobile cloud computing code offload context migration distributed shared memory virtual machine

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CGUW: A System Software for Heterogeneous IPC Mechanism in Grid Computing Environments 23

CGUW: A System Software for Heterogeneous IPC Mechanism in G...

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23rd International Conference on Engineering, Technology and Innovation (ICE/ITMC)

作者： Khaneghah, Ehsan Mousavi Ghoreishi, Seyed Ali Shahed Univ Dept Comp Engn Tehran Iran

ISBN: (纸本)9781538607749

Interprocess communication mechanisms, one of the effective factors for response time in High performance computing. Existing standards for interprocess communication between a heterogeneous operating systems such as MPI implementation at library level lead to lower performance and Increase response time compared to implementation at the operating system kernel level. We propose an approach to enable the use of IPC in heterogeneous distributed systems such as grid computing. This mechanism uses distributed shared memory for communication between Linux and Windows operating systems. Windows IPC mechanism uses shared memory and remote procedural call. Linux Inter-zprocess communication (IPC) converting Windows remote procedure call (RPC) to Proportional System V shared memory in kernel level. We propose wrapper for the use of our mechanism with distributed application.

关键词： Interprocess communication distributed shared memory Wrapper Kernel Level

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An Improved Algorithm About Failure Agreement Based on distributed shared memory

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Procedia Engineering 2011年 15卷 3330-3334页

作者： Jun Wang Yaqiong Jiang Financial Department Guilin University of Electronic Technology China Network Information Center Guilin University of Electronic Technology China

关键词： distributed shared memory Failure Agreement Algorithm Security Parallelism

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Exploring the Assessment of the DSM-5 Alternative Model for Personality Disorders With the Personality Assessment Inventory

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JOURNAL OF PERSONALITY ASSESSMENT 2017年第2期99卷 211-218页

作者： Busch, Alexander J. Morey, Leslie C. Hopwood, Christopher J. Texas A&M Univ Dept Psychol 282 Psychol Bldg College Stn TX 77843 USA Michigan State Univ Dept Psychol E Lansing MI 48824 USA

Section III of the Diagnostic and Statistical Manual of Mental Disorders (5th ed. [DSM-5];American Psychiatric Association, 2013) contains an alternative model for the diagnosis of personality disorder involving the assessment of 25 traits and a global level of overall personality functioning. There is hope that this model will be increasingly used in clinical and research settings, and the ability to apply established instruments to assess these concepts could facilitate this process. This study sought to develop scoring algorithms for these alternative model concepts using scales from the Personality Assessment Inventory (PAI). A multiple regression strategy used to predict scores in 2 undergraduate samples on DSM-5 alternative model instruments: the Personality Inventory for the DSM-5 (PID-5) and the General Personality Pathology scale (GPP;Morey etal., 2011). These regression functions resulted in scores that demonstrated promising convergent and discriminant validity across the alternative model concepts, as well as a factor structure in a cross-validation sample that was congruent with the putative structure of the alternative model traits. Results were linked to the PAI community normative data to provide normative information regarding these alternative model concepts that can be used to identify elevated traits and personality functioning level scores.

关键词： PERSONALITY tests PERSONALITY disorder diagnosis distributed shared memory STUDY & teaching of psychodiagnostics REGRESSION analysis

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Region Based Cache Coherence for Tiled MPSoCs 30

Region Based Cache Coherence for Tiled MPSoCs

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30th IEEE International System-on-Chip Conference (SOCC)

作者： Srivatsa, Akshay Rheindt, Sven Wild, Thomas Herkersdorf, Andreas Tech Univ Munich Chair Integrated Syst Munich Germany

ISBN: (纸本)9781538640340

The need for faster and more energy efficient computing has led us to the multicore era with distributed shared memory hierarchies. The primary goal is to distribute parallel tasks onto multiple processing elements to collectively achieve shorter execution times at lower frequencies and supply voltages when compared to a single-core architecture. Major challenges of this approach are how to achieve local, low latency memory accesses and low overheads for coherence and synchronization management. We believe that enabling global coherence in tiled many-core architectures does not scale in a cost efficient manner and isn't even required for applications with limited degrees of parallelism. In this paper, we propose a novel region based cache coherence scheme, where coherence is provided by hardware directories within a flexibly sized but confined set of compute and memory tiles. We also show that data placement and task mapping have a huge impact on the application performance, and hence should be considered in conjunction with region based coherence. The approach is evaluated by means of a high level simulation model using workloads from PARSEC. Experiments demonstrate that our region based approach with multiple compute tiles increases performance by a factor of up to 2.5 compared to a single tile structure with nominally identical computing and memory resources. Thus the independent local memory accesses, which are effectively increasing the memory bandwidth, usually outweigh the penalties of inter-tile remote memory accesses. Our approach also reduces the directory structures significantly compared to traditional schemes, making it scalable for large MPSoCs (eg. by 41.4% for a 16 tile system with 4 tiles per region). Considering data-to-task-placement, our investigations show that it can lead to performance variations up to a factor of 12.7.

关键词： cache coherence dynamic coherency regions distributed shared memory scalable multicore architectures

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