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MICROPROCESSORS AND MICROSYSTEMS 2016年第PartB期47卷 262-277页

作者： Alvarez, Carlos Ayguade, Eduard Bosch, Jaume Bueno, Javier Cherkashin, Artem Filgueras, Antonio Jimenez-Gonzalez, Daniel Martorell, Xavier Navarro, Nacho Vidal, Miquel Theodoropoulos, Dimitris Pnevmatikatos, Dionisios N. Catani, Davide Oro, David Fernandez, Carles Segura, Carlos Rodriguez, Javier Hernando, Javier Scordino, Claudio Gai, Paolo Passera, Pierluigi Pomella, Alberto Bettin, Nicola Rizzo, Antonio Giorgi, Roberto Univ Politecn Cataluna Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Comp Architecture Dept Barcelona Spain FORTH ICS Iraklion Greece SECO Arezzo Italy Herta Secur Barcelona Spain Univ Politecn Cataluna Barcelona Spain Evidence Srl Pisa Italy VIMAR SpA Marostica Italy Univ Siena Siena Italy

People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping alow power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed. The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics). (C) 2016 The Authors. Published by Elsevier B.V.

关键词： Cyber-physical systems Ompss Cluster programming FPGA Programming distributed shared memory Smart home Smart video-surveillance

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An OpenMP Programming Toolkit for Hybrid CPU/GPU Clusters Based on Software Unified memory

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JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 2016年第3期32卷 517-539页

作者： Li, Hung-Fu Liang, Tyng-Yeu Lin, Yu-Jie Natl Kaohsiung Univ Appl Sci Dept Elect Engn Kaohsiung 807 Taiwan

Recently, hybrid CPU/GPU cluster has drawn much attention from the researchers of high performance computing because of amazing energy efficiency and adaptable resource exploitation. However, the programming of hybrid CPU/GPU clusters is very complex because it requires users to learn new programming interfaces such as CUDA and OpenCL, and combine them with MPI and OpenMP. To address this problem, we propose a novel OpenMP toolkit called HyCOMP (Hybrid Cluster OpenMP) for hybrid CPU/GPU clusters in this paper. This toolkit is developed based on a novel page-based distributed shared memory system called SUM (software unified memory) which is aimed at emulating a virtual shared memory space over distributed CPUs and GPUs. Compared to traditional page-based DSM systems, SUM can effectively prevent GPUs from performance degradation caused by the latency of handling an enormous number of page faults coming from host-to-device memory copies. Moreover, HyCOMP can automatically achieve load balance of heterogeneous processors. Consequently, HyCOMP dramatically reduces the programming complexity of hybrid CPU/GPU clusters while simultaneously maintains the execution performance of user programs.

关键词： hybrid CPU/GPU cluster OpenMP distributed shared memory page-based pre-fetching load balance

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Predicting the performance measures of an optical distributed shared memory multiprocessor by using support vector regression

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EXPERT SYSTEMS WITH APPLICATIONS 2010年第9期37卷 6293-6301页

作者： Akay, M. Fatih Abasikeles, Ipek Cukurova Univ Dept Comp Engn Adana Turkey

Recent advances in the development of optical technologies suggest the possible emergence of optical interconnects within distributed shared memory (DSM) multiprocessors. The performance of these DSM architectures must be evaluated under varying values of DSM parameters. In this paper, we develop a Support Vector Regression (SVR) model for predicting the performance measures (i.e. average network latency, average channel waiting time and average processor utilization) of a DSM multiprocessor architecture interconnected by the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus), which is a high-bandwidth, fiber-optic interconnection network. The basic idea is to collect a small number of data points by using a statistical simulation and predict the performance measures of the system for a large set of input parameters based on these. OPNET Modeler is used to simulate the DSM-based SOME-Bus multiprocessor architecture and to create the training and testing datasets. The prediction error and correlation coefficient of the SVR model is compared to that of Multiple Linear Regression (MLR) and feedforward Artificial Neural Network (ANN) models. Results show that the SVR-RBF model has the lowest prediction error and is more robust. It is concluded that SVR model shortens the time quite a bit for obtaining the performance measures of a DSM multiprocessor and can be used as an effective tool for this purpose. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： Support vector regression Multiprocessors distributed shared memory Interconnection networks

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LUC Model : A Timestamp Ordering based View Consistency Model for distributed shared memory

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JOURNAL OF COMPUTERS 2010年第12期5卷 1828-1838页

作者： Rafat, Rubaiyat Islam Sakib, Kazi Univ Dhaka Inst Informat Technol Informat Technol Dhaka Bangladesh Univ Dhaka Inst Informat Technol Dhaka Bangladesh

Excessive locking and cumulative updates in distributed shared memory (DSM) not only reduces the parallelism for block access but also causes a serious degradation in response time for a dense network. This paper proposes a new consistency model in DSM named Last Update Consistency (LUC) model, where the model uses logical clock counter to keep the DSM consistent. The logical clock always increases never decreases. So the increasing order of the logical clock value is used to provide the request to the DSM. In this model, multiple nodes can perform READ operations over the same block at a time. For WRITE operation over the same block, only the last modification will exist and the earlier WRITE operations will be treated as obsolete WRITE and should be discarded. The experimental and analytical analysis showed that the proposed model effectively reduces the unnecessary network traffic and cumulative block updates that exist in the Sequential Consistency Model and Release Consistency Model.

关键词： View Consistency Model Timestamp Ordering Protocol distributed shared memory

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Interconnect Emulator for Aiding Performance Analysis of distributed memory Applications 7

Interconnect Emulator for Aiding Performance Analysis of Dis...

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7th ACM/SPEC International Conference on Performance Engineering (ICPE)

作者： Wang, Qi Cherkasova, Ludmila Li, Jun Volos, Haris Hewlett Packard Labs Palo Alto CA 94304 USA George Washington Univ Washington DC 20052 USA

ISBN: (纸本)9781450340809

Many modern large graph and Big Data processing applications operate on datasets that do not fit into DRAM of a single machine. This leads to a design of scale-out applications, where the application dataset is partitioned and processed by a cluster of machines. Typically, these applications rely on high speed interconnects which employ Remote Direct memory Access (RDMA) technology to provide fast and high bandwidth communications. distributed memory applications exhibit complex behavior: they tend to interleave computations and communications, use bursty transfers, and utilize global synchronization primitives. This makes it difficult to analyze the impact of communication layer on the application performance and answer the questions: how interconnect latency or bandwidth characteristics may change the application performance? will the application performance scale when processed by a larger system? In this work,(1) we introduce a novel emulation framework, called InterSense, which is implemented on top of existing high-speed interconnect, such as InfiniBand, and which provides two performance knobs for changing the (today's) interconnect bandwidth and latency. This approach offers an easy-to-use framework for a sensitivity analysis of complex distributed applications to communication layer performance instead of creating customized and time-consuming application models to answer the same questions. We evaluate the emulator accuracy with popular OSU MPI benchmark suite and two clusters with different generation InfiniBand interconnects (DDR and FDR): InterSense emulates the specified bandwidth and latency values with less than 2% error between the expected and measured values. InterSense supports an efficient emulation of a wide range of interconnect latencies and bandwidth characteristics for enabling performance and scalability analysis of Big Data applications, deriving and interpolating their requirements for performance characteristics of the underlying commun

关键词： Performance emulation InfiniBand MPI distributed shared memory benchmarking profiling

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AXIOM: A Hardware-Software Platform for Cyber Physical Systems 19

AXIOM: A Hardware-Software Platform for Cyber Physical Syste...

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19th Euromicro Conference on Digital System Design (DSD)

作者： Mazumdar, Somnath Ayguade, Eduard Bettin, Nicola Bueno, Javier Ermini, Sara Filgueras, Antonio Jimenez-Gonzalez, Daniel Alvarez Martinez, Carlos Martorell, Xavier Montefoschi, Francesco Oro, David Pnevmatikatos, Dionisis Rizzo, Antonio Theodoropoulos, Dimitris Giorgi, Roberto Univ Siena Dipartimento Ingn Informaz & Sci Matemat I-53100 Siena Italy Barcelona Supercomp Ctr Barcelona Spain VIMAR SpA Marostica Marostica Italy Univ Siena Dipartimento Sci Sociali Polit & Cognit I-53100 Siena Italy Univ Politecn Catalunya Barcelona Comp Architecture Dept Barcelona Spain Herta Secur Barcelona Barcelona Spain Fdn Res & Technol Hellas FORTH Crete Inst Comp Sci Iraklion Greece Tech Univ Crete Sch ECE Khania Greece

ISBN: (纸本)9781509028160

Cyber-Physical Systems (CPSs) are widely necessary for many applications that require interactions with the humans and the physical environment. A CPS integrates a set of hardware-software components to distribute, execute and manage its operations. The AXIOM project (Agile, eXtensible, fast I/O Module) aims at developing a hardware-software platform for CPS such that i) it can use an easy parallel programming model and ii) it can easily scale-up the performance by adding multiple boards (e.g., 1 to 10 boards can run in parallel). AXIOM supports task-based programming model based on OmpSs and leverage a high-speed, inexpensive communication interface called AXIOM-Link. Another key aspect is that the board provides programmable logic (FPGA) to accelerate portions of an application. We are using smart video surveillance, and smart home living applications to drive our design.

关键词： Cyber-physical systems distributed shared memory programming model performance evaluation reconfigurable smart video surveillance smart home living

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shared memory Tile-Based vs Hybrid memory GOP-Based Parallel Algorithms for HEVC Encoder 16th

Shared Memory Tile-Based vs Hybrid Memory GOP-Based Parallel...

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16th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP)

作者： Migallon, Hector Lopez-Granado, Otoniel Galiano, Vicente Pinol, Pablo Malumbres, Manuel P. Miguel Hernandez Univ Dept Phys & Comp Architecture Avda Univ S-N Alicante 03202 Spain

ISBN: (纸本)9783319495835;9783319495828

After the emergence of the new High Efficiency Video Coding standard, several strategies have been followed in order to take advantage of the parallel features available in it. Many of the parallelization approaches in the literature have been performed in the decoder side, aiming at achieving real-time decoding. However, the most complex part of the HEVC codec is the encoding side. In this paper, we perform a comparative analysis of two parallelization proposals. One of them is based on tiles, employing shared memory architectures and the other one is based on Groups Of Pictures, employing distributed shared memory architectures. The results show that good speed-ups are obtained for the tile-based proposal, especially for high resolution video sequences, but the scalability decreases for low resolution video sequences. The GOP-based proposal outperforms the tile-based proposal when the number of processes increases. This benefit grows up when low resolution video sequences are compressed.

关键词： HEVC Video coding Parallel encoding shared memory distributed shared memory

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Brief Announcement: Locally-Accessible Implementations for distributed shared memory Multiprocessors

Brief Announcement: Locally-Accessible Implementations for D...

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29th ACM SIGACT-SIGOPS Symposium on Principles of distributed Computing

作者： Golab, Wojciech Univ Calgary Dept Comp Sci Calgary AB T2N 1N4 Canada

ISBN: (纸本)9781605588889

We consider asynchronous multiprocessors that support the distributed shared memory (DSM) model. Algorithms for such multiprocessors exploit the ability to co-locate shared objects with particular processes in order to reduce the cost of accessing shared memory. When a shared object fits inside a single memory word and operations on it are supported directly through machine instructions, it can be made local to any process simply by fixing its physical address. We show that even if the shared object is not supported in hardware directly, it can always be simulated using a software implementation that behaves as though it is local to some designated process. That is, operations applied by the designated process on the implemented object access only local base objects, which is non-trivial when processes synchronize by busy-waiting. We also discuss time complexity bounds for such locally-accessible implementations.

关键词： distributed shared memory remote memory references shared objects locally-accessible implementations

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The Designing and Implementing of distributed shared memory

The Designing and Implementing of Distributed Shared Memory

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International Conference on Innovative Computing and Communication/Asia-Pacific Conference on Information Technology and Ocean Engineering

作者： Wang Chengduan WeiFang Univ Dept Comp Sci & Technol Weifang Peoples R China

ISBN: (纸本)9780769539423

The distributed shared memory is used to manage the memory in distributed system. In this paper, we have studied the DSM, modified the structure of DSM, and have designed and implemented it. In unstructured DSM, The key issues are the granularity of data, transfers, replication of data, memory consistence, and keeping track of the data throughout the system. In implementing of structured DSM, we have researched DSM with weak consistency, DSM with release or entry consistency, and object-based DSM.

关键词： distributed shared memory Replication Granularity consistency

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Symbolic Prefetching in Transactional distributed shared memory

Symbolic Prefetching in Transactional Distributed Shared Mem...

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15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

作者： Dash, Alokika Demsky, Brian Univ Calif Irvine Irvine CA 92717 USA

ISBN: (纸本)9781605587080

We present a static analysis for the automatic generation of symbolic prefetches in a transactional distributed shared memory. A symbolic prefetch specifies the first object to be prefetched followed by a list of field offsets or array indices that define a path through the heap. We also provide an object caching framework and language extensions to support our approach. To our knowledge, this is the first prefetching approach that can prefetch objects whose addresses have not been computed or predicted. Our approach makes aggressive use of both prefetching and caching of remote objects to hide network latency. It relies on the transaction commit mechanism to preserve the simple transactional consistency model that we present to the developer. We have evaluated this approach on several shared memory parallel benchmarks and a distributed gaming benchmark to observe speedups due to prefetching and caching.

关键词： Symbolic prefetching Transactional memory distributed shared memory

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