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检索条件"主题词=distributed shared memory"

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Software distributed shared memory with Transactional Coherence A software engine to run transactional shared-memory parallel applications on clusters

Software Distributed Shared Memory with Transactional Cohere...

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18th Euromicro International Conference on Parallel, distributed and Network-Based Processing (PDP)

作者： Di Santo, Michele Ranaldo, Nadia Sementa, Carmine Zimeo, Eugenio Univ Sannio Dept Engn Benevento Italy

ISBN: (纸本)9780769539393

Transactional memory is a novel, promising approach for simplifying parallel programming and increasing its acceptance and diffusion. Until now, almost all the research work on TM has been focused on shared-memory architectures, while very limited effort has been dedicated to TM on distributed-memory architectures. In this paper, we propose an extension of the transactional engine DSTM2, originally designed for hardware shared-memory systems, so as to run transactional applications on the nodes of a computer cluster. The framework obtained provides a software distributed shared memory with transactional consistency whereby threads running on the nodes of a cluster can access a shared memory with atomicity and isolation. So the physical private memory of each node contributes to form a global address space accessible through programming statements having transactional semantics. The extension proposed is also useful for experimentally evaluating different techniques to be employed in a distributed implementation of TM.

关键词： transactional memory commodity clusters distributed shared memory scalability

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Exploring Dataflow-based Thread Level Parallelism in Cyber-Physical Systems (invited paper) 16

Exploring Dataflow-based Thread Level Parallelism in Cyber-P...

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ACM International Conference on Computing Frontiers (CF)

作者： Giorgi, Roberto Univ Siena Dept Informat Engn & Math Siena Italy

ISBN: (纸本)9781450341288

Smart Cyber-Physical Systems (SCPS) aim not only at integrating computational platforms and physical processes, but also at creating larger "systems of systems" capable of satisfying multiple critical constraints such as energy efficiency, high-performance, safety, security, size and cost. The AXIOM project aims at designing such systems by focusing on low-cost Single Board Computers (SBC), based on current System-on-Chips (SoC) that include both programmable logic (FPGA), multi-core CPUs, accelerators and peripherals. A dataflow execution model, partially developed in the TERAFLUX project, brings a more predictable and reliable execution. The goals of AXIOM include: i) the possibility to easily program the system with a shared-memory model based on OmpSs;ii) the possibility of scaling up the system through a custom but inexpensive interconnect;iii) the possibility of accelerating a specific function on a single or multiple FPGAs of the system. The dataflow execution model operates at thread-level granularity. In this paper the AXIOM execution model and the related memory memory model is further detailed. The memory model is key for the execution of threads while reducing the need of data transfers. The preliminary results confirm the scalability of this model.

关键词： Thread-Level Parallelism Dataflow Cyber-Physical System Scalability distributed shared memory Programming Model

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A Bounded memory Allocator for Software-Defined Global Address Spaces 2016

A Bounded Memory Allocator for Software-Defined Global Addre...

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15th ACM SIGPLAN International Symposium on memory Management (ISMM 2016)

作者： Gindraud, Francois Rastello, Fabrice Cohen, Albert Broquedis, Francois UJF Grenoble France INRIA Paris France Grenoble INP Grenoble France

ISBN: (纸本)9781450343176

This paper presents a memory allocator targeting manycore architectures with distributed memory. Among the family of Multi Processor System on Chip (MPSoC), these devices are composed of multiple nodes linked by an on-chip network;most nodes have multiple processors sharing a small local memory. While MPSoC typically excel on their performance-per-Watt ratio, they remain hard to program due to multilevel parallelism, explicit resource and memory management, and hardware constraints (limited memory, network topology). Typical programming frameworks for MPSoC leave much target-specific work to the programmer: combining threads or node-local OpenMP, software caching, explicit message passing (and sometimes, routing), with non-standard interfaces. More abstract, automatic frameworks exist, but they target large-scale clusters and do not model the hardware constraints of MPSoC. The memory allocator described in this paper is one component of a larger runtime system, called Givy, to support dynamic task graphs with automatic software caching and data-driven execution on MPSoC. To simplify the programmer's view of memory, both runtime and program data objects live in a Global Address Space (GAS). To avoid address collisions when objects are dynamically allocated, and to manage virtual memory mappings across nodes, a GAS-aware memory allocator is required. This paper proposes such an allocator with the following properties: (1) it is free of inter-node synchronizations;(2) its node-local performance match that of state-of-the-art shared-memory allocators;(3) it provides node-local mechanisms to implement inter-node software caching within a GAS;(4) it is well suited for small memory systems (a few MB per node).

关键词： memory allocation global address space distributed shared memory

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JCL: A High Performance Computing Java Middleware 18

JCL: A High Performance Computing Java Middleware

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18th International Conference on Enterprise Information Systems (ICEIS)

作者： Barroso Almeida, Andre Luis Delabrida Silva, Saul Emanuel Nazare, Antonio C., Jr. Lima, Joubert de Castro Univ Fed Ouro Preto DECOM Ouro Preto MG Brazil Univ Fed Ouro Preto CODAAUT Ouro Preto MG Brazil Univ Fed Minas Gerais DCC Belo Horizonte MG Brazil

ISBN: (纸本)9789897581878

Java Ca&La or just JCL is a distributed shared memory reflective lightweight middleware for Java developers whose main goals are: i) provide a simple deployment strategy, where automatic code registration occurs, ii) support a collaborative multi-developer cluster environment where applications can interact without explicit dependencies, iii) execute existing sequential Java code over both multi-core machines and cluster of multi-core machines without refactorings, enabling the separation of business logic from distribution issues in the development process, iv) provide a multi-core/ multi-computer portable code. This paper describes JCL's features and architecture;compares and contrasts JCL to other Java based middleware systems, and reports performance measurements of JCL applications.

关键词： Big Data Internet of Things Middleware Reflective Computing High Performance Computing distributed shared memory Remote Method Invocation

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An Interval Constrained memory Allocator for the Givy GAS Runtime 16

An Interval Constrained Memory Allocator for the Givy GAS Ru...

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21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Gindraud, Francoise Rastello, Fabrice Cohen, Albert Broquedis, Francoise UJF St Martin Dheres France Inria Rocquencourt France Grenoble INP Grenoble France

ISBN: (纸本)9781450340922

The shared memory model helps parallel programming productivity, but it also has a high hardware cost and imposes scalability constraints. Ultimately, higher performance will use distributed memories, which scales better but requires programmers to manually transfer data between local memories, which is a complex task. distributed memories are also more energy efficient than shared memories, and are used in a family of embedded computing solutions called multi processor system on chip (MPSoC).

关键词： memory allocation global address space distributed shared memory

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Interconnect Emulator for Aiding Performance Analysis of distributed memory Applications 16

Interconnect Emulator for Aiding Performance Analysis of Dis...

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Proceedings of the 7th ACM/SPEC on International Conference on Performance Engineering

作者： Qi Wang Ludmila Cherkasova Jun Li Haris Volos George Washington University Washington DC USA Hewlett Packard Labs Palo Alto USA

ISBN: (纸本)9781450340809

Many modern large graph and Big Data processing applications operate on datasets that do not fit into DRAM of a single machine. This leads to a design of scale-out applications, where the application dataset is partitioned and processed by a cluster of machines. distributed memory applications exhibit complex behavior: they tend to interleave computations and communications, use bursty transfers, and utilize global synchronization primitives. This makes it difficult to analyze the impact of communication layer on the application performance and answer the questions: how interconnect latency or bandwidth characteristics may change the application performance will the application performance scale when processed by a larger system? In this work, we introduce a novel emulation framework, called InterSense, which is implemented on top of existing high-speed interconnect, such as InfiniBand, and which provides two performance knobs for changing the (today's) interconnect bandwidth and latency. This approach offers an easy-to-use framework for a sensitivity analysis of complex distributed applications to communication layer performance instead of creating customized and time-consuming application models to answer the same questions. We evaluate the emulator accuracy with popular OSU MPI benchmark suite and two clusters with different generation InfiniBand interconnects (DDR and FDR): InterSense emulates the specified andwidth and latency values with less than 2% error between the expected and measured values. To demonstrate the InterSense's ease of use, we present a case study, where we apply InterSense for sensitivity analysis of four applications and benchmarks for getting non-trivial insights.

关键词： infiniband benchmarking performance emulation distributed shared memory MPI profiling

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Overview of IO Queuing Algorithm in distributed memory

Overview of IO Queuing Algorithm in Distributed Memory

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2016 International Congress on Computation Algorithms in Engineering

作者： Feng Gao Wancheng Luo Changyang Li School of Software Engineering Chongqing University of Arts and Sciences School of Computer Science Beijing Institute of Technology

The distributed shared memory system provides a development road for establishment of a large-scale easy-to-use parallel computer, and the improvement of its corresponding algorithm can optimize the distributed shared memory. This paper mainly summarizes the spatial data memory system and parallel processing methods, thus providing the specific theoretical guidance for the parallel spatial data memory and processing. This paper also analyzes and improves the basic distributed shared IO algorithm of the central server algorithm, migration algorithm, read-replication algorithm and full-replication algorithm, and then focuses on discussion of the consistency model of the distributed shared memory, and analyzes the direction of using different consistency models, and points out the shortcomings of traditional methods to store and process massive spatial data, thus providing a theoretical direction for the future improvement of the memory.

关键词： distributed shared memory automatic fault tolerance communication consumption

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Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing 13

Scalable Embedded Systems: Towards the Convergence of High-P...

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13th International Conference on Embedded and Ubiquitous Computing (EUC 2015)

作者： Giorgi, Roberto Univ Siena Siena Italy

ISBN: (纸本)9781467382991

Embedded System toolchains are highly customized for a specific System-on-Chip (SoC). When the application needs more performance, the designer is typically forced to adopt a new SoC and possibly another toolchain. The rationale for not scaling performance by using, e.g., two SoCs, is that maintining most of the operations on-chip may allow for higher energy efficiency. We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC. This board is based on FPGAs and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards. A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer. In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach.

关键词： Cyber-Physical Systems Reconfigurable Systems Cluster Programming FPGA Programming distributed shared memory Programming Model Performance Evaluation

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The AXIOM Software Layers 18

The AXIOM Software Layers

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18th Euromicro Conference on Digital System Design (DSD)

作者： Alvarez, Carlos Ayguade, Eduard Bueno, Javier Filgueras, Antonio Jimenez-Gonzalez, Daniel Martorell, Xavier Navarro, Nacho Theodoropoulos, Dimitris Pnevmatikatos, Dionisios N. Scordino, Claudio Gai, Paolo Catani, Davide Segura, Carlos Fernandez, Carles Oro, David Saeta, Javier Rodriguez Passera, Pierluigi Pomella, Alberto Rizzo, Antonio Giorgi, Roberto Barcelona Supercomp Ctr Dept Comp Sci Barcelona Spain Univ Politecn Cataluna Comp Architecture Dept Barcelona Spain FORTH ICS Hellas Greece Evidence Srl Pisa Italy SECO Arezzo Italy Herta Secur Barcelona Spain VIMAR SpA Marostica Italy Univ Siena Siena Italy

ISBN: (纸本)9781467380355

People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed. The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics).

关键词： cyber-physical systems OmpSs Cluster Programming FPGA Programming distributed shared memory Smart Home Smart Video-surveillance

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OPCAM: Optimal Algorithms Implementing Causal Memories in shared memory Systems 15

OPCAM: Optimal Algorithms Implementing Causal Memories in Sh...

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16th International Conference on distributed Computing and Networking

作者： Shen, Min Kshemkalyani, Ajay D. Hsu, Ta-yuan Univ Illinois Chicago IL 60607 USA

ISBN: (纸本)9781450329286

Data replication is commonly used for fault tolerance in reliable distributed systems. In this paper, we propose three optimal protocols for causal consistency in distributed shared memory systems. Our proposed optimal protocols are designed for partial replication across the distributed shared memory. Complete replication is a special case of our protocols and we also give the optimal implementation of causal consistency for the complete replication case. Algorithm Full-Track is optimal in the sense that it can update the local copy as soon as possible while respecting causal consistency. Algorithm Opt-Track is further optimal in the sense that the size of the local logs maintained and the amount of control information piggybacked on the update messages is minimal. Algorithm Opt-Track-CRP is a special case of algorithm Opt-Track for the full replication case. It is highly scalable, and significantly more efficient than the Baldoniet al. protocol for the complete replication case.

关键词： causal consistency distributed shared memory causality replication

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