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Overview of Center for domain-specific computing

Journal of Computer Science & Technology 2011年第4期26卷 632-635页

作者：丛京生 Center for Domain-Specific Computing University of California

In this short article, we would like to introduce the Center for domain-specific computing （CDSC） established in 2009, primarily funded by the US National Science Foundation with an award from the 2009 Expeditions in computing Program. In this project we look beyond parallelization and focus on customization as the next disruptive technology to bring orders-of-magnitude power-performance efficiency improvement for applications in a specific domain.

关键词： domain-specific computing customization reconfigurable computing heterogeneous platforms

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High-level Synthesis for domain specific computing 23

High-level Synthesis for Domain Specific Computing

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International Symposium on Physical Design (ISPD)

作者： Ye, Hanchen Jun, Hyegang Yang, Jin Chen, Deming Univ Illinois Champaign IL 61801 USA Intel Santa Clara CA 95054 USA

ISBN: (纸本)9781450399784

This paper proposes a High-Level Synthesis (HLS) framework for domain-specific computing. The framework contains three key components: 1) ScaleHLS, a multi-level HLS compilation flow. Aimed to address the lack of expressiveness and hardware-dedicated representation of traditional software-oriented compilers. ScaleHLS introduces a hierarchical intermediate representation (IR) for the progressive optimization of HLS designs defined in various high-level languages. ScaleHLS consists of three levels of optimizations, including graph, loop, and directive levels, to realize an efficient compilation pipeline and generate highly-optimized domain-specific accelerators. 2) AutoScaleDSE is an automated design space exploration (DSE) engine. Real-world HLS designs often come with large design spaces that are difficult for designers to explore. Meanwhile, the connections between different components of an HLS design further complicate the design spaces. In order to address the DSE problem, AutoScaleDSE proposes a random forest classifier and a graph-driven approach to improve the accuracy of estimating the intermediate DSE results while reducing the time and computational cost. With this new approach, AutoScaleDSE can evaluate thousands of HLS design points and find the Pareto-dominating design points within a couple of hours. 3) PyTransform is a flexible pattern-driven design customization flow. Existing HLS flows demand manual code rewriting or intrusive compiler customization to conduct domain-specific optimizations, leading to unscalable or inflexible compiler solutions. PyTransform proposes a Python-based flow that enables users to define custom matching and rewriting patterns at a high level of abstraction, being able to be incorporated into the DSL compilation flow in an automatic and scalable manner. In summary, ScaleHLS, AutoScaleDSE, and PyTransform aim to address the challenges present in the compilation, DSE, and customization of existing HLS flows, respectively. Wit

关键词： HLS domain-specific language domain-specific computing MLIR design space exploration

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domain-specific Many-core computing using Spin-based Memory

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2014年第5期13卷 881-894页

作者： Venkatesan, Rangharajan Chippa, Vinay K. Augustine, Charles Roy, Kaushik Raghunathan, Anand Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47906 USA Intel Corp Circuit Res Labs Hillsboro OR 97124 USA

Spin-based devices have shown great potential in enabling high-density, energy-efficient memory and are therefore, considered highly promising for the design of future computing platforms. While the impact of spin-based devices on general-purpose computing platforms has been studied, they are yet to be explored in the context of domain-specific computing, where the characteristics of the devices can be matched to application characteristics through architectural customization, so as to maximize the benefits. We present the design and evaluation of a many-core domain-specific processor for the emerging application domains of Recognition and Mining (RM) using spin-based memories. The domain-specific processor has a two-level on-chip memory hierarchy consisting of a streaming access first-level memory and a random access second-level memory. Based on the memory access characteristics, we suggest the use of domain Wall Memory (DWM) and Spin Transfer Torque Magnetic RAM (STT-MRAM) to realize the first and second levels, respectively. We develop architectural models of DWM and STT-MRAM, and use them to evaluate the proposed design and explore various architectural tradeoffs in the domain-specific processor. We evaluate the proposed design by comparing it to a CMOS-based baseline at the same technology node. For three representative RM algorithms (support vector machine, k-means clustering, and generalized learning vector quantization), the spin-memory-based design achieves an energy-delay product improvement of 1.5x-4x over the CMOS baseline at iso-area. Our results suggest that spin-based memory technologies can enable significant improvements in energy efficiency and performance for highly parallel, data-intensive workloads. Our study also highlights the importance of synergistic architectural exploration along with the use of emerging devices rather than simply considering them as drop-in replacements.

关键词： domain-specific computing many-core processor spin-based memory

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Platform Feminism: Celebrity Culture and Activism in the Digital Age

Platform Feminism: Celebrity Culture and Activism in the Dig...

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作者： Lawson, Caitlin E. University of Michigan

学位级别：Ph.D.

Platform Feminism: Celebrity Culture and Activism in the Digital Age tells the story of digital platforms' role in the feminist movement during the early 21st century. Taking celebrity culture as a potent site at which to analyze the new visibilities of feminism and its responses to a new wave of conservative and deeply reactionary politics, I explore the ways in which networked publics coalesce around celebrity events and, in discussing, analyzing, and critiquing various actors within these events, engage in boundary work around what it means to “be a feminist.” From responses to celebrity harassment to hashtag campaigns supporting celebrity feminism to critiques of imperfect feminist celebrities, this dissertation explores the contentious debates about feminism that arise around celebrity culture within digital spaces. To analyze these discourses, this project draws together literature from three often-disparate academic subfields: platform studies, feminist media studies, and celebrity studies. Using a case study approach, each chapter draws on intersectional feminist theory to examine a celebrity event from 2014-2016 that incited controversy across a variety of media platforms around issues of gender, sexuality, race, and class. I track each event across online and legacy media outlets and engage in multiplatform critical technocultural discourse analysis to analyze how discussions amongst issue publics that coalesce around each event both reflect and further define contemporary feminist discourses in ways that are often distinctly shaped by the digital platforms on which they emerge (Burgess & Matamoros-Fernández 2016, Brock 2016). In contrast to prior feminist media studies research that argues popular culture is largely postfeminist, I demonstrate that feminism, amplified by the famous voices that espouse it and the broad reach of the digital spaces in which it appears, has increased its discursive power so greatly that many aspects of popular culture no long

关键词： AI domain-specific computing hardware acceleration integrated circuit design processor architecture software architecture Electrical Engineering Engineering

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Stream Processing Dual-Track CGRA for Object Inference

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2018年第6期26卷 1098-1111页

作者： Fan, Xitian Wu, Di Cao, Wei Luk, Wayne Wang, Lingli Fudan Univ State Key Lab Applicat Specif Integrated Circuit Shanghai 201203 Peoples R China Imperial Coll London Dept Comp London SW7 2AZ England

With the development of machine learning technology, the exploration of energy-efficient and flexible architectures for object inference algorithms is of growing interest in recent years. However, not many publications concentrate on a coarse-grained reconfigurable architecture (CGRA) for object inference algorithms. This paper provides a stream processing, dual-track programming CGRA-based approach to address the inherent computing characteristics of algorithms in object inference. Based on the proposed approach, an architecture called stream dual-track CGRA (SDT-CGRA) is presented as an implementation prototype. To evaluate the performance, the SDT-CGRA is realized in Verilog HDL and implemented in Semiconductor Manufacturing International Corporation 55-nm process, with the footprint of 5.19 mm(2) at 450 MHz. Seven object inference algorithms, including convolutional neural network (CNN), k-means, principal component analysis (PCA), spatial pyramid matching (SPM), linear support vector machine (SVM), Softmax, and Joint Bayesian, are selected as benchmarks. The experimental results show that the SDT-CGRA can gain on average 343.8 times and 17.7 times higher energy efficiency for Softmax, PCA, and CNN, 621.0 times and 1261.8 times higher energy efficiency for k-means, SPM, linear-SVM, and Joint-Bayesian algorithms when compared with the Intel Xeon E5-2637 CPU and the Nvidia TitanX graphics processing unit. When compared with the state-of-the-art solutions of AlexNet on field-programmable gate array and CGRA, the proposed SDT-CGRA can achieve a 1.78 times increase in energy efficiency and a 13 times speedup, respectively.

关键词： Acceleration coarse-grained reconfigurable architecture (CGRA) deep learning domain-specific computing object inference

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Integrated Analog Computers as domain-specific Accelerators: A Tutorial Review 67

Integrated Analog Computers as Domain-Specific Accelerators:...

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67th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Mandal, Soumyajit Liang, Jifu Malavipathirana, Hasantha Udayanga, Nilan Silva, Hiruni Hariharan, S., I Madanayake, Arjuna Brookhaven Natl Lab Instrumentat Dept Upton NY 11973 USA Case Western Reserve Univ Elect Comp & Syst Engn Cleveland OH 44106 USA Florida Int Univ Elect & Comp Engn Miami FL 33174 USA

ISBN: (纸本)9798350387186;9798350387179

Recent innovations in devices, circuits, and systems have resulted in the widespread use of parallel and in-memory architectures for energy-efficient computing. However, the choice of signal representation within these architectures has received less attention. Nevertheless, computing using analog variables is known to be fundamentally more resource-efficient for low- and moderate-precision operations, making it of interest for applications, such as inference and real-time control, where high precision is not a requirement. However, well-known difficulties with scalability, programambility, and memory access have impeded the realization of integrated analog computers (ACs) that can utilize these fundamental advantages. This paper provides a tutorial-style review of state-of-the-art integrated ACs and their advantages, including ultra-low latency and high energy-efficiency, for solving selected problems where clocked digital architectures are not resource-efficient.

关键词： Analog computing hardware acceleration domain-specific computing PDE solvers

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DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architecture for Stream Applications 26

DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architectu...

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26th International Conference on Field-Programmable Logic and Applications (FPL)

作者： Fan, Xitian Li, Huimin Cao, Wei Wang, Lingli Fudan Univ State Key Lab ASIC & Syst 825 Zhangheng Rd Shanghai 201203 Peoples R China

ISBN: (纸本)9782839918442

This paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. The proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. The CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm(2) and consuming 1.79 W at 500 MHz. To evaluate the performance, eight machine-learning algorithms including HOG, CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. These algorithms cover a general machine learning flow in object inference domain: feature extraction, feature selection and inference. The experimental results show that the proposed CGRA can gain 1443x average energy efficiency comparing to the Intel i7-3770 CPU and 7.82x energy efficiency comparing to a high performance FPGA solution [19].

关键词： coarse-grained reconfigurable architecture domain-specific computing machine learning object inference

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CHIME: Energy-Efficient STT-RAM-based Concurrent Hierarchical In-Memory Processing 35

CHIME: Energy-Efficient STT-RAM-based Concurrent Hierarchica...

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35th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

作者： Gajaria, Dhruv Adegbija, Tosiron Gomez, Kevin Univ Arizona Dept Elect & Comp Engn Tucson AZ 85004 USA Univ Massachusetts Dept Comp Sci Amherst MA 01003 USA

ISBN: (纸本)9798350349641;9798350349634

Processing-in-cache (PiC) and Processing-in-memory (PiM) architectures, especially those utilizing bit-line computing, offer promising solutions to mitigate data movement bottlenecks within the memory hierarchy. While previous studies have explored the integration of compute units within individual memory levels, the complexity and potential overheads associated with these designs have often limited their capabilities. This paper introduces a novel PiC/PiM architecture, Concurrent Hierarchical In-Memory Processing (CHIME), which strategically incorporates heterogeneous compute unitsacross multiple levels of the memory hierarchy. This design targets the efficient execution of diverse, domain-specific workloads by placing computations closest to the data where it optimizes performance, energy consumption, data movement costs, and area. CHIME employs STT-RAM due to its various advantages in PiC/PiM computing, such as high density, low leakage, and better resiliency to data corruption from activating multiple word lines. We demonstrate that CHIME enhances concurrency and improves compute unit utilization at each level of the memory hierarchy. We present strategies for exploring the design space, grouping, and placing the compute units across the memory hierarchy. Experiments reveal that, compared to the state-of-the-art bit-line computing approaches, CHIME achieves significant speedup and energy savings of 57.95% and 78.23% for various domain-specific workloads, while reducing the overheads associated with single-level compute designs.

关键词： Processing-in-cache (PiC) Processing-in-memory (PiM) concurrency hierarchical computing STT-RAMs domain-specific computing

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Accelerating Design and Implementation of Embedded Vision Systems

Accelerating Design and Implementation of Embedded Vision Sy...

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作者： Al Maashri, Ahmed PennState University Libraries

学位级别：Doctor of Philosophy

In today’s world, embedded systems have become a necessity in our daily lives. Ranging from digital watches to factory controllers, these systems are dedicated to handle a particular task both efficiently and reliably. The advancements in computer vision and machine learning, in conjunction with the abundance of computational power, made it possible for these systems to perform other tasks such as image processing and video analytics; giving rise to embedded vision systems. Being the heart of embedded vision systems, computer vision is the key technology enabler for image processing and video analytics. However, the computational modalities that are prominent in computer vision algorithms are usually inconsistent with those modalities most exploited in contemporary computer architectures. As a result, execution inefficiencies are observed when algorithms are processed by such architectures. Furthermore, recent studies have shown that biologically-inspired (neuromorphic) vision algorithms can be robust alternatives, due to their detection and recognition capabilities. Interestingly, these neuromorphic algorithms experience similar execution inefficiencies when running on general purpose *** the other hand, domain-specific computing is believed to be the solution to the challenges presented above. Developing customized hardware accelerators targeting specific workloads, is the key to achieving the desired performance while operating at a lower power budget. However, domain-specific computing may be an unfavorable route to many, due to a whole host of challenges associated with hardware design and *** dissertation addresses the issues presented above by describing a hardware-software framework that offers a flexible, reliable, and high performance accelerator infrastructure. The underlying hardware complexity of the framework is abstracted from the user through a standardized Application Programming Interface, API. Furthermore, the dissertatio

关键词： Embedded Vision Systems domain-specific computing Reconfigurable computing Power Efficiency Neuromophic Accelerators

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