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检索条件"主题词=dual-rail code"

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Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices 13

Fault-Tolerant Finite State Machine Quasi Delay Insensitive ...

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13th Latin America Symposium on Circuits and System (LASCAS)

作者： Verducci, Orlando Oliveira, Duarte L. Batista, Gracieth Technol Inst Aeronaut Elect Engineer Div ITA Sao Jose Dos Campos SP Brazil

ISBN: (纸本)9781665420082

because electronic devices cannot avoid soft errors (unexpected and non- destructive signal transitions) occurred in radiation environment, circuit redundancy approaches are adopted for such situations, which lead to huge penalties in area and power dissipation resources in digital design. QDI-AFSM (Quasi-Delay Insensitive-Asynchronous Finite State Machine), which uses dual-rail variables, may be an interesting solution for fault-tolerant digital systems if some additional circuitry is used for soft errors detection. In FPGA, this issue is particularly concerning because, in such target devices, any digital circuitry is modeled using programmable LUTs (Look Up Tables) where a flipped bit cannot be recovered unless a new programming procedure be done. The proposed architecture for finite state machines in FPGA devices enhances robustness to a QDI digital design inserting a novel output register based on sequential logic gates that validate each dual-rail output variable on the system according to the current processing cycle and output state. The reduced average penalties in area, power, and latency for the proposed fault-tolerant architecture may be advantageous compared to TMR approaches.

关键词： dual-rail code asynchronous circuit fault-tolerant QDI state machine XBM soft error SEU SET

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Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA 13

Design of Asynchronous Pipelines with QDI Template Using Com...

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13th Latin America Symposium on Circuits and System (LASCAS)

作者： Duarte, Gabriel C. Oliveira, Duarte L. Batista, Gracieth C. Inst Tecnol Aeronaut ITA Div Engn Eletron IEEA Sao Jose Dos Campos Brazil

ISBN: (纸本)9781665420082

The asynchronous paradigm has interesting features due to the lack of the clock signal and is another option for project of digital systems. This paradigm has several design styles, where the asynchronous pipeline style is interesting due to its high performance and the simplicity of its control. There are two classes of an asynchronous pipeline: Bundled-data and Quasi Delay Insensitive (QDI). The QDI circuit class is notable for its robustness and high modularity. In this paper, we propose two new asynchronous architectures in the pipeline style for QDI circuits. Unlike many QDI proposals, these architectures focus on platforms FPGA (Field Programmable Gate Array) and VLSI (Very Large-Scale Integration) standard cell. The two new architectures were prototyped in FPGAs devices, applied in a set of benchmarks, and compared with the literature's QDI pipeline architecture, which is also focused on FPGA. From the results obtained by the three architectures, we highlight the increase in throughput of 51.2% of the proposed architecture compared to the literature's architecture.

关键词： QDI asynchronous logic dual-rail code pipeline

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Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices 22

Fault-Tolerant Quasi Delay Insensitive Combinational Circuit...

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22nd IEEE Latin American Test Symposium (LATS)

作者： Verducci, Orlando Oliveira, Duarte L. Moreno, Robson L. Technol Inst Aeronaut Elect Engn Div Sao Jose Dos Campos Brazil Univ Fed Itajuba IESTI Itajuba MG Brazil

ISBN: (纸本)9781665420570

Fault tolerance design is an increasing concern due to VLSI technology scaling, which implements more complex systems in a single chip. Each transistor in such systems is more susceptible to the effects of high-energy particle strikes, mainly in reduced power supply applications. Glitches in any node of the circuit caused by a soft error may propagate or even captured by a memory cell components. In FPGA, this issue is particularly concerning because, in such target devices, any digital circuitry is modeled using programmed LUTs (Look Up Tables) where a flipped bit cannot be recovered unless new programming on it. The proposed architecture for combinational circuits in FPGA devices enhances robustness to a QDI (Quasi-Delay Insensitive) digital design inserting a novel output register based on gates that validate each dual-rail variable the system according to the current processing cycle. The reduced penalties in area, power, and latency for the proposed fault-tolerant architecture are interesting compared to Triple Modular Redundancy (TMR), and dual Modular Redundancy (DMR) approaches.

关键词： dual-rail code asynchronous logic fault-tolerant QDI control soft error SEU SET

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A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication 12

A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensi...

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12th IEEE Latin America Symposium on Circuits and System (LASCAS)

作者： Oliveira, Duarte L. Duarte, Gabriel C. Batista, Gracieth C. Inst Tecnol Aeronaut ITA IEEA Div Engn Eletron Sao Jose Dos Campos SP Brazil

ISBN: (纸本)9781728176703

Nowadays, digital circuits are implemented in the Ultra Deep-Sub-Micron (UDSM) MOS technology. In UDSM-MOS technology, communication between subsystems may require several clock cycles, bringing about the communication of the two senses, an increasing penalty in latency and power. The QDI (Quasi Delay Insensitive) asynchronous circuits class is a design alternative in UDSM-MOS technology because this class does not use a clock signal, so it eliminates the problems related to the clock signal and is highly robust to PVT (process, supply voltage, and temperature) variations, which is pertinent to UDSM-MOS technology, due to its greater variability. Usually, the QDI class operates on the four-phase protocol, but this incurs a cost in communication between subsystems. In this paper, we propose a new asynchronous QDI pipeline architecture. Unlike other proposals, this architecture performs the communication with the environment is carried out using the QDI LEDR (Level-Encoded dual-rail) protocol, which is two-phase, therefore allows in communication a reduction in latency and power when compared to the QDI protocol of four phases. Through a case study, we show the efficiency of the new QDI pipeline.

关键词： QDI asynchronous logic dual-rail code LEDR code pipeline speed-independent control circuit

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Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools 33

Implementation of Asynchronous Pipelines with QDI Template o...

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33rd Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Oliveira, Duarte L. Duarte, Gabriel C. Cardoso, Nicolly N. M. Batista, Gracieth C. Inst Tecnol Aeronaut ITA IEEA Div Engn Eletron Sao Jose Dos Campos SP Brazil

ISBN: (纸本)9781728196251

The asynchronous paradigm has unusual characteristics due to the lack of the clock signal, being another option for the design of digital systems. This paradigm has several classes of circuits. The QDI circuit class (Quasi Delay Insensitive) is notable for its robustness and high modularity. In this paper, we propose a new asynchronous architecture in the pipeline style for QDI circuits. Unlike many QDI proposals, this architecture is focused on FPGA (Field Programmable Gated Array) platform. We also present an approach based on the platform of commercial tools aimed at FPGAs. Where through a case study, we investigated the implementation of the QDI pipeline in commercial FPGAs. Despite low throughput and a high area, there is a satisfactory dissipated power and remains with all the robustness properties.

关键词： QDI asynchronous logic dual-rail code pipeline

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A High Performance Implementation of Quasi Delay Insensitive Booleans Functions 26

A High Performance Implementation of Quasi Delay Insensitive...

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IEEE 26th International Conference on Electronics, Electrical Engineering and Computing (INTERCON)

作者： Oliveira, Duarte L. Verducci, Orlando Batista, Gracieth C. Curtinhas, Tiago S. Technol Inst Aeronaut ITA Elect Engn Div ILEA Sao Jose Dos Campos SP Brazil Adventist Univ Ctr Sao Paulo Unasp Dept Comp Sci Sao Paulo Brazil

ISBN: (纸本)9781728136462

Digital circuit design demands critical requirements such as power consumption, robustness, performance, etc. when it is implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features aiming to solve these requirements. An important class of asynchronous paradigm is the so-called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for those kinds of applications because they are robust to noise, to temperature variations, to wire and gate delays and to supply voltage variation, having also low electromagnetic emissions. QDI combinational circuits are designed as function blocks whose indicatability shows the robustness of the circuit communication with the environment. This paper presents two architectures based on basic gates and C elements as also an approach to the synthesis of the QDI function blocks. The two new architectures were prototyped in FPGAs (Field Programmable Gated Array) devices, applied in a set of benchmarks and compared with other architectures of the literature. Our proposal shows respectively a gain of up to 18.6%, 53.1%, 40.7% and 51.8% in latency, number of LUTs and power, dynamic and static, respectively.

关键词： asynchronous logic QDI circuits dual-rail code

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A Design Flow for Synthesis of Quasi Delay Insensitive Combinational Circuits

A Design Flow for Synthesis of Quasi Delay Insensitive Combi...

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IEEE International Congress on Electronics, Electrical Engineering and Computing (INTERCON)

作者： Vitor L. V. Torres Duarte L. Oliveira Gracieth C. Batista Orlando Verducci Electronic Engineering Division – IEEA Technological Institute of Aeronautics – ITA São José dos Campos São Paulo Brazil

ISBN: (数字)9781728193779

ISBN: (纸本)9781728193786

Nowadays, synchronous digital circuits design in MOS technology can cause difficulties, this is due to the clock signal. The asynchronous paradigm presents interesting features focused on to solve the clock signal problem. An important class of the asynchronous paradigm is the known Quasi Delay Insensitive (QDI) circuits that can also be used for critical applications, because they are robust to temperature variations, to wire and gate delays, and to supply voltage variation, having low electromagnetic emissions and low noise. QDI combinational circuits are designed as a block of functions whose indicability shows the robustness of the circuit communication with the environment. This paper presents an architecture based on basic gates that do not use C-elements to implement QDI functions. In addition, an approach to the synthesis of QDI function blocks and a disjoint logic minimization method (DSOP) for simple output. The new architecture as the DSOP method has been tested for a set of benchmarks. We can highlight the area reduction of up to 64.3% compared to literature QDI architectures.

关键词： asynchronous logic QDI circuits dual-rail code asynchronous logic Combinational circuits Design flow synthesis MOS Technology clock signal new buildings ARCHITECTURE Function

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A Tools Flow for Extended Burst-Mode State Machines Design with Enhanced Robustness

A Tools Flow for Extended Burst-Mode State Machines Design w...

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IEEE International Congress on Electronics, Electrical Engineering and Computing (INTERCON)

作者： Duarte L. Oliveira Orlando Verducci Gracieth C. Batista Diego A. Silva Electronic Engineer Division – IEEA Technological Institute of Aeronautics – ITA São Paulo Brazil

ISBN: (数字)9781728193779

ISBN: (纸本)9781728193786

Due to the increasing demand for mobile devices and CMOS-UDSM (Ultra Deep Sub-Micron) technology, the search for ultra-low-power projects is becoming a priority. One technique that allows a substantial reduction of circuits consumed power is the sub-threshold voltage operation, but it leads to some drawbacks. The Speed Independent asynchronous circuits show an interesting solution to operate at sub-threshold voltage because they satisfy the unbounded delay gate model. However, there is a limitation with UDSM technology because the wires have zero delays. In this paper, we propose an architecture and approach that synthesizes asynchronous finite state machines (AFSM) with enhanced robustness. They are described by the extended burst-mode (XBM) specification. The resulting XBM_AFSMs are flexible QDI (Quasi Delay Insensitive), so they can operate within sub-threshold voltage and in UDSM technology because they interact with the environment in flexible weak-indication mode. The approach is presented through the case study, and the XBM_AFSMs synthesized show a good optimization when compared to XBM_AFSMs from the literature.

关键词： AFSM SI circuits synthesis dual-rail code synthesis state machines VOLTAGE Mobile devices threshold voltage Power consumption ELECTRIC WIRE Electric circuits

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A Four-Phase dual-rail Protocol based Asynchronous Arbiter for Neuromorphic Networks 9

A Four-Phase Dual-Rail Protocol based Asynchronous Arbiter f...

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9th International Conference on Intelligent Human-Machine Systems and Cybernetics (IHMSC)

作者： Chen, Longlong Ying, Zhaozhong Luo, Chong Zhu, Xiaolei Zhejiang Univ Inst VLSI Design Hangzhou Zhejiang Peoples R China

ISBN: (纸本)9781538630228

This paper presents a quasi-delay-insensitive(QDI) asynchronous arbiter that uses dual-rail(DR) code and four-phase handshake protocol. It is useful to make non-deterministic selection from multiple DR encoded input data channels for neuromorphic networks, in which several events often occur concurrently. This design consists of three sub-modules with standard and universal architecture and thus it is easy to be extended for arbitrarily more input channels. The proposed arbiter is implemented by standard 0.18 mu m CMOS technology with 1.8V power supply. The simulation results show that the average latency for data transmission is 2.8ns.

关键词： Quasi-delay-insensitve Arbiter dual-rail code Asynchronous circuit

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