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ASAver.1: An FPGA-based education board for computer architecture system design

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND computer SCIENCES 1997年第10期E80A卷 1826-1833页

作者： Ochi, H Kamidoi, Y Kawabata, H Faculty of Information Sciences Hiroshima City University Hiroshima-shi 731-31 Japan

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a pipelined RISC processor within Limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model;it has separate buses for instruction and data memory (''Harvard architecture'') to avoid structural hazard, while it completely ignores data and control hazards to make implementation easy. Although it is such a ''defective'' processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally, every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ri SA rer. I which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor ''ASAP-0'' has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions. From feasibility study result, it is shown that ASAP-0 is described by just 310 lines of Verilog-HDL, and it is implemented to an FPGA device XC5215 with about 1.5-hour runtime of CAD tools. ASAP-0 is so compact that even it can be implemented within a so-called 6,000-gateclass FPGA device XC5206. The proposed education approach has been applied to our department in the last semester, and all of 53 students have completed the experiments successfully.

关键词： education of computer architecture system design DLX-like pipelined RISC processor field-programmable gate array verilog-HDL

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