检索结果-内蒙古大学图书馆

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： K.C. Chang C.A. Lomasney Boeing ISDS Seattle WA USA

A methodology is proposed which encompasses the design, simulation, synthesis and layout of obsolete digital parts using EDA technologies that are currently available to cutting edge ASIC and FPGA designers. The approach described herein provides a means for exploiting the efficiencies afforded by design automation technologies, while meeting the functional performance, timing and area requirements of obsolete designs. In addition, a methodology for integrating multiple designs on one die is presented which reduces cost and maximizes gate density for small obsolete designs. This paper outlines in detail how functional, timing and layout requirements for obsolete parts can be met specifically using Hardware Description Languages (HDL) and advanced electronics design automation (EDA) Tools from Mentor Graphics, Synopsys and Cascade design automation.

关键词： electronic design automation and methodology design automation Timing Hardware design languages Circuit simulation Integrated circuit synthesis Integrated circuit technology Application specific integrated circuits Field programmable gate arrays Costs

来源：评论

学校读者我要写书评

暂无评论

Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED design OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第5期44卷 1954-1967页

作者： Vanna-Iampikul, Pruek Woo, Seungmin Erdogan, Serhat Zhu, Lingjun Kathaperumal, Mohanalingam Agarwal, Ravi Gupta, Ram Rinebold, Kevin Swaminathan, Madhavan Lim, Sung Kyu Burapha Univ Dept Elect Engn Chon Buri 20131 Thailand Georgia Inst Technol Dept Elect & Comp Engn Atlanta GA 30332 USA Meta Platforms Inc Dept Adv Technol Dev Menlo Pk CA 94025 USA Siemens Ind Software Inc Adv Packaging Solut Dept Plano TX 75024 USA Penn State Univ Dept Elect Engn University Pk PA 16802 USA

Glass interposers have become a compelling option for 2.5-D heterogeneous integration compared to silicon. It allows 3-D stacking configuration between the embedded dies and the conventional flip-chip dies mounted directly on top at low cost. Furthermore, the interconnect pitch and through-glass-via (TGV) diameter in glass are becoming comparable to their counterparts in silicon. In this study, we investigate the power, performance, area (PPA), signal integrity (SI) and power integrity (PI) advantages of 3-D stacking afforded by glass interposers over silicon interposers. Our research employs a chiplet/package co-design approach, progressing from an register-transfer-level description of RISC-V chiplets to final graphic data system (GDS) layouts, utilizing TSMC 28 nm for chiplets and Georgia Tech's 3-D glass packaging for the interposer. Compared to silicon, glass interposers offer a 2.6x reduction in area, a 21x reduction in wire length, a 17.72% reduction in full-chip power consumption, a 64.7% increase in SI and a 10x improvement in PI, with a 35% increase in thermal. Furthermore, we provide a detailed comparative analysis with 3-D Silicon technologies. It not only highlights the competitive advantages of glass interposers, but also provides critical insights into each design's potential limitations and optimization opportunities.

关键词： Glass Chiplets Silicon Three-dimensional displays Stacking Logic Substrates Integrated circuits Costs Wire 2.5-D integrated circuits 3-D integrated circuits chiplets electronic design automation and methodology signal integrity thermal analysis

来源：评论

学校读者我要写书评

暂无评论

Using GPUs to Accelerate CAD Algorithms

IEEE DESIGN & TEST

引用

IEEE design & TEST 2013年第1期30卷 8-16页

作者： Croix, John F. Gulati, Kanupriya Khatri, Sunil P. Intel Corp Strateg CAD Lab Santa Clara CA 95051 USA Texas A&M Univ College Stn TX 77843 USA

The authors give an introduction to developing an EDA tool on a graphical processing unit. They present fault simulation as one of their EDA-specific examples.

关键词： European Defence Agency DFFB gene electronic design automation EDA gene PROCESSOR Computer-Aided design acceleration annonacin-A-one Writers algorithms electronic design automation and methodology PROCESS UNITS fault simulation

来源：评论

学校读者我要写书评

暂无评论

Looking into the Crystal Ball: From Transistors to the Smart Earth

IEEE DESIGN & TEST

引用

IEEE design & TEST 2014年第2期31卷 47-55页

作者： Sangiovanni-Vincentelli, Alberto Sciuto, Donatella Politecn Milan Milan Italy

Presents a look at technological innovations from transistors to current smart technologies.

关键词： electronic design automation and methodology design automation Technology Forecasting Transistors electronics Smart Devices

来源：评论

学校读者我要写书评

暂无评论

Integrating Machine-Learning Probes in FPGA CAD: Why and How?

IEEE DESIGN & TEST

引用

IEEE design & TEST 2023年第5期40卷 7-14页

作者： Martin, Timothy Barnes, Charlotte Grewal, Gary Areibi, Shawki Univ Guelph Sch Comp Sci Guelph ON N1G 2W1 Canada Univ Guelph Sch Engn Guelph ON N1G 2W1 Canada

This article discusses challenges posed by current designs and proposes the adoption of machine-learning probes in the FPGA design flow to improve performance.

关键词： Field programmable gate arrays Routing Probes Video recording Wires Benchmark testing Machine learning electronic design automation and methodology EDA FPGA Machine Learning

来源：评论

学校读者我要写书评

暂无评论

Sociology of design and EDA

引用

IEEE design & TEST OF COMPUTERS 2006年第4期23卷 304-310页

作者： Rhines, Walden C. Mentor Graph Corp Wilsonville OR 97070 USA

Walden C. Rhines, CEO and chairman of the board of Mentor Graphics, delivered this keynote address at the design, automation, and Test in Europe Conference and Exhibition (DATE 06).

关键词： Sociology electronic design automation and methodology Companies design automation Europe Automatic Testing Graphics Ecosystems History Voting EDA DATE Conference

来源：评论

学校读者我要写书评

暂无评论

Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第2期70卷 715-720页

作者： Zhu, Keren Chen, Hao Liu, Mingjie Pan, David Z. Univ Texas Austin Dept Elect & Comp Engn Austin TX 78713 USA

MAGICAL is an open-source system for analog and mixed-signal (AMS) circuit layout synthesis. Using custom place-and-route and constraint extraction algorithms, MAGICAL provides a fully-automated layout implementation flow. MAGICAL 1.0 has been proven in silicon with a 40-nm 1GS/s AI ADC. The source code has been released to enable broad usage. Recently, MAGICAL has also been extended to cover more circuit classes such as SAR-ADC. This tutorial/perspective paper describes the overall MAGICAL framework and algorithms. We also provide a tutorial on how to use and extend MAGICAL and discuss future research directions for AMS layout design automation.

关键词： Layout Routing Tutorials Pins Engines Python Performance evaluation electronic design automation and methodology design automation CADCAM

来源：评论

学校读者我要写书评

暂无评论

Calibrating simulation tools for nanometer designs

引用

IEEE SPECTRUM 1999年第6期36卷 77-82页

作者： Shahram, M EPIC Technol Grp Synopsys Inc R&D Characterizat & Modelling Mt View CA USA

Deals with the method employed by the Direct Silicon Access laboratory of Synopsys Inc. in Mountain View, California for preparing calibrated models or technology files for foundry processes using a lookup table (LUT). Importance of calibrated simulation tools to integrated circuit designers; Advantages of LUT; Limitations of spice-like simulators or analytical models.

关键词： Silicon electronic design automation and methodology Circuit simulation System-on-a-chip Feeds Transistors Integrated circuit interconnections Manufacturing processes Virtual manufacturing Calibration

来源：评论

学校读者我要写书评

暂无评论

Theory and computation of electromagnetic transition matrix elements in the continuous spectrum of atoms

引用

EUROPEAN PHYSICAL JOURNAL D 2017年第1期71卷 1-13页

作者： Komninos, Yannis Mercouris, Theodoros Nicolaides, Cleanthes A. Natl Hellen Res Fdn Theoret & Phys Chem Inst 48 Vasileos Constantinou Ave Athens 11635 Greece

The present study examines the mathematical properties of the free-free (f-f) matrix elements of the full electric field operator, O-E (kappa, (r) over right arrow), of the multipolar Hamiltonian. kappa is the photon wavenumber. Special methods are developed and applied for their computation, for the general case where the scattering wavefunctions are calculated numerically in the potential of the term-dependent (N - 1) electron core, and are energy-normalized. It is found that, on the energy axis, the f - f matrix elements of O-E(kappa, (r) over right arrow) have singularities of first order, i.e., as epsilon' -> epsilon, they behave as (epsilon - epsilon')(-1). The numerical applications are for f - f transitions in hydrogen and neon, obeying electric dipole and quadrupole selection rules. In the limit kappa = 0, O-E(kappa, (r) over right arrow) reduces to the length form of the electric dipole approximation (EDA). It is found that the results for the EDA agree with those of O-E (kappa, (r) over right arrow), with the exception of a wave-number region k' = k +/- kappa about the point k' = k.

关键词： matrices Elements electronic design automation matrix theories continuous spectra electronic design automation and methodology electric dipole ENERGY-LEVEL TRANSITIONS arithmetic Matrix Element Atoms EDA gene European Defence Agency Neon

来源：评论

学校读者我要写书评

暂无评论

MODEL COIL FOR THE INTERNATIONAL THERMONUCLEAR EXPERIMENTAL REACTOR (ITER) MAGNET SYSTEMS

引用

IEEE TRANSACTIONS ON MAGNETICS 1994年第4期30卷 1621-1626页

作者： OKUNO, K ITER Joint Central and Home Teams Ibaraki-ken Jpn

The model coil program for the ITER EDA includes the manufacture and testing of one Central Solenoid (CS) model coil and one Toroidal Field (TF) model coil, and test facility preparations. The CS model coil has an inner diameter of 1.6 m and produces a full field of 13 T. The TF model coil is race-track shaped with an outer dimension of 3 m x 4 m. It will be tested in conjunction with an LCT coil to simulate mechanical load conditions. Different kinds of conductors can be tested as inserts to be placed in the bore of the CS model coil. Two facilities at JAERI and KfK can provide ITER-relevant conditions for testing the model coils and inserts. The model coil program will validate the ITER magnet design and the manufacturing feasibility.

关键词： Coils Inductors Testing Virtual manufacturing electronic design automation and methodology Solenoids Test facilities Conductors Boring Toroidal magnetic fields

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：