Worst case execution time (WCET) analysis is essential for exposing timeliness defects when developing hard real-time systems. However, it is too late to fix timeliness defects cheaply since developers generally perfo...
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Worst case execution time (WCET) analysis is essential for exposing timeliness defects when developing hard real-time systems. However, it is too late to fix timeliness defects cheaply since developers generally perform WCET analysis in a final veri fication phase. To help developers quickly identify real timeliness defects in an early programming phase, a novel interactive WCET prediction with warning for timeout risk is proposed. The novelty is that the approach not only fast estimates WCET based on a control flow tree (CFT), but also assesses the estimated WCET with a trusted level by a lightweight false path analysis. According to the trusted levels, corresponding warnings will be triggered once the estimated WCET exceeds a preset safe threshold. Hence developers can identify real timeliness defects more timely and efficiently. To this end, we first analyze the reasons of the overestimation of CFT-based WCET calculation;then we propose a trusted level model of timeout risks;for recognizing the structural patterns of timeout risks, we develop a risk data counting algorithm;and we also give some tactics for applying our approach more effectively. Experimental results show that our approach has almost the same running speed compared with the fast and interactive WCET analysis, but it saves more time in identifying real timeliness defects.
java has gained great popularity in embedded appliances such as set-top boxes, smart phones and other hand held devices. In this paper we propose a translation based hw/sw codesigned java virtual machine architecture,...
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java has gained great popularity in embedded appliances such as set-top boxes, smart phones and other hand held devices. In this paper we propose a translation based hw/sw codesigned java virtual machine architecture, which extends a typical embedded RISC processor. The architectural extensions we propose include special instructions that accelerate translated blocks dispatch and security checks for arrays and objects. The extensions are done in a way that operating systems support is maintained, something that makes their adoption more attractive. Benchmarking using embedded Caffeine Mark (ECM) benchmarks, showed significant speedups, especially when high performance RISC processors are employed. (C) 2009 Elsevier B.V. All rights reserved.
Though java was first used in an embedded system,due to some technical reasons java language is not widely applied to embedded *** change the situation, Sun defines some new java specifications for embedded applicatio...
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Though java was first used in an embedded system,due to some technical reasons java language is not widely applied to embedded *** change the situation, Sun defines some new java specifications for embedded application *** the Real-Time Specification for java(RTSJ)proposed,more and more programmers begin to devote to real-time java *** paper gives an overview of java-based embedded real-time systems and analyzes future work about java-based embedded real-time technology.
In this paper, we discuss the origin, design, performance, and directions of the inAspect high-performance signal- and image-processing package for java. The Vector Signal and Image Processing Library (VSIPL) communit...
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In this paper, we discuss the origin, design, performance, and directions of the inAspect high-performance signal- and image-processing package for java. The Vector Signal and Image Processing Library (VSIPL) community provides a standardized application programmer interface (API) for high-performance signal and image processing plus linear algebra with a C emphasis and object-based design framework. java programmers need high-performance and/or portable APIs for this broad base of functionality as well. inAspect addresses PDAs, embedded java boards, workstations, and servers, with emphasis on embedded systems at present. Efforts include supporting integer precisions and utilizing coordinate rotation digital computer (CORDIC) algorithms-both aimed at added relevance for limited-performance environments, such as present-day PDAs. Copyright (c) 2005 John Wiley & Sons, Ltd.
Limited energy and memory resources are important constraints in the design of an embedded system. Compression is an useful and widely employed mechanism to reduce the memory requirements of the system. As the leakage...
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ISBN:
(纸本)1581135424
Limited energy and memory resources are important constraints in the design of an embedded system. Compression is an useful and widely employed mechanism to reduce the memory requirements of the system. As the leakage energy of a memory system increases with its size and because of the increasing contribution of leakage to overall system energy, compression also has a significant effect on reducing energy consumption. However, storing compressed data/instructions has a performance and energy overhead associated with decompression at runtime. The underlying compression algorithm, the corresponding implementation of the decompression and the ability to reuse decompressed information critically impact this overhead. In this paper, we explore the influence of compression on overall memory energy using a commercial embedded java virtual machine (JVM) and a customized compression algorithm. Our results show that compression is effective in reducing energy even when considering the runtime decompression overheads for most applications.
A 32bit java-based processor is designed for mobile multimedia applications to run MIPS-compatible local instructions and some application-specific java bytecodes in a RISC-like architecture. In java-mode, some java b...
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ISBN:
(纸本)0780377494
A 32bit java-based processor is designed for mobile multimedia applications to run MIPS-compatible local instructions and some application-specific java bytecodes in a RISC-like architecture. In java-mode, some java bytecodes employed in the specific application are decoded into local instructions by VLSI implementation. With VHDL simulation tools, SW\HW co-design verified that java bytecodes could be executed on the processor with a local thread for a real-time visual processing. Furthermore, the design was synthesized to physical layout according to 1.2mum standard CMOS technology and the simulation shows that the processor can run at a frequency of 20MHz.
Autonomous underwater vehicles (AUVs) have a great potential use for the United States Marine Corps and United States Navy. When performing amphibious operations, underwater mines present a danger for t he forces goin...
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Autonomous underwater vehicles (AUVs) have a great potential use for the United States Marine Corps and United States Navy. When performing amphibious operations, underwater mines present a danger for t he forces going ashore. The use of underwater vehicles for the detection of this mines and signaling to the Amphibious Ready Group is very attractive. With advancements in hardware and object oriented language technology, more complicated and robust software can be developed. The Naval Postgraduate School Center for AUV Research has been designing, building, operating, and researching AUVs since 1987. Each generation of vehicles has provided substantially increased in operational capabilities and level of sophistication in the hardware and software respectively. With the advancement in real-time computer languages support, object oriented technology, and cost efficient and high performance hardware, this thesis lays the foundations to develop a software system for the execution level using the java language. We look into the java Real-Time specifications and extension to familiarize with the capabilities of java for real-time support, and study java boards and its application for embedded real-time systems. We developed an object-oriented design for the execution level control software and implemented the design in java. A testing phase is still under work.
In this paper, we discuss the origin, design, performance, and directions of the inAspect high-performance signal and image processing package for java. The Vector Signal and Image Processing (VSIPL) community provide...
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ISBN:
(纸本)9781581135992
In this paper, we discuss the origin, design, performance, and directions of the inAspect high-performance signal and image processing package for java. The Vector Signal and Image Processing (VSIPL) community provides a standardized API (Application Programmer Interface) for high-performance signal and image processing plus linear algebra with a C emphasis and object-based design framework. java programmers need high performance and/or portable APIs for this broad base of functionality as well. InAspect addresses PDA's, embedded java boards, workstations, and servers, with emphasis on embedded systems at present. Efforts include supporting integer precisions and utilizing CORDIC algorithms, both aimed at added relevance for limited-performance environments, such as present-day PDAs.
作者：
Montague, BRLaboratory of Chromatography
DEPg.Fac.Quimica Universidad Nacional Autonoma de Mexico Circuito interior Cd Universitaria/CP 04510 Mexico D.F.Mexico
Presents information on the development of a custom embedded computer operating system to support the java Virtual Machine (JVM), focusing on javaSoft's OS. Information on when the system was developed; Who develo...
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Presents information on the development of a custom embedded computer operating system to support the java Virtual Machine (JVM), focusing on javaSoft's OS. Information on when the system was developed; Who developed the system; Reference to other systems under development by java; Background information on JVM systems. INSETS: Traditional OS engineering lessons revisited.;Helpful URLs..
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