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22nd International Conference on Microelectronics (ICM 2010)

作者： Sieler, Loic Derutin, Jean Pierre Damez, Lionel Landrault, Alexis Univ Clermont Ferrand LASMEA CNRS UMR 6602 Clermont Ferrand France

ISBN: (纸本)9781612841519

This article proposes an original methodology for the fast prototyping of image processing on a generic MP-SoC (Multi-Processors System on Chip) architecture. To define a processors network adapted to a particular application is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability of an ad hoc design methodology. This paper illustrates a new methodology that enables to instantiate a generic Homogeneous Network of Communicating Processors (called HNCP) tailored for a targeted application. The HNCP is generated with a tool that avoids fastidious manual editing operations for the designer. Specific lightweight communication functions have been developed to fasten the programming of the MP-SoC network. A case study (image texture analyzes) is presented to illustrate the proposed MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

关键词： ad hoc design methodology architecture exploration embedded image processing fast prototyping generic MP-SoC design methodology homogeneous network of communicating processors image texture image texture analyzes microprocessor chips multiprocessors syste

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Implementation of Thermal Event image processing Algorithms on NVIDIA Tegra Jetson TX2 embedded System-on-a-Chip

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ENERGIES 2021年第15期14卷

作者： Jablonski, Bartlomiej Makowski, Dariusz Perek, Piotr Lodz Univ Technol Dept Microelect & Comp Sci PL-90924 Lodz Poland

Advances in Infrared (IR) cameras, as well as hardware computational capabilities, contributed towards qualifying vision systems as reliable plasma diagnostics for nuclear fusion experiments. Robust autonomous machine protection and plasma control during operation require real-time processing that might be facilitated by Graphics processing Units (GPUs). One of the current aims of image plasma diagnostics involves thermal events detection and analysis with thermal imaging. The paper investigates the suitability of the NVIDIA Jetson TX2 Tegra-based embedded platform for real-time thermal events detection. Development of real-time processing algorithms on an embedded System-on-a-Chip (SoC) requires additional effort due to the constrained resources, yet low-power consumption enables embedded GPUs to be applied in MicroTCA.4 computing architecture that is prevalent in nuclear fusion projects. For this purpose, the authors have proposed, developed and optimised GPU-accelerated algorithms with the use of available software tools for NVIDIA Tegra systems. Furthermore, the implemented algorithms are evaluated and benchmarked on Wendelstein 7-X (W7-X) stellarator experimental data against the corresponding alternative Central processing Unit (CPU) implementations. Considerable improvement is observed for the accelerated algorithms that enable real-time detection on the embedded SoC platform, yet some encountered limitations when developing parallel image processing routines are described and signified.

关键词： embedded image processing graphics processing unit tegra thermal event real-time algorithm plasma diagnostics

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A Resource-Efficient Hardware Architecture for Connected Component Analysis

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2016年第7期26卷 1334-1349页

作者： Klaiber, Michael J. Bailey, Donald G. Baroud, Yousef O. Simon, Sven Univ Stuttgart Inst Parallel & Distributed Syst D-70174 Stuttgart Germany Massey Univ Palmerston North 4442 New Zealand

A resource-efficient hardware architecture for connected component analysis (CCA) of streamed video data is presented, which reduces the required hardware resources, especially for larger image widths. On-chip memory requirements increase with image width and dominate the resources of state-of-the-art CCA single-pass hardware architectures. A reduction in on-chip memory resources is essential to meet the ever increasing image sizes of high-definition (HD) and ultra-HD standards. The proposed architecture is resource efficient due to several innovations. An improved label recycling scheme detects the last pixel of an image object in the video stream only a few clock cycles after its occurrence, allowing the reuse of a label in the following image row. The coordinated application of these techniques leads to significant memory savings of more than two orders in magnitude compared with classical two-pass connected component labeling architectures. Compared with the most memory-efficient state-of-the-art single-pass CCA hardware architecture, 42% or more of on-chip memory resources are saved depending on the features extracted. Based on these savings, it is possible to realize an architecture processing video streams of larger images sizes, or to use a smaller and more energy-efficient field-programmable gate array device, or to increase the functionality of already existing image processing pipelines in reconfigurable computing and embedded systems.

关键词： Connected component analysis (CCA) connected component labeling (CCL) embedded image processing field-programmable gate array (FPGA) parallel architecture

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Mobile image sensors for object detection using color segmentation

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CLUSTER COMPUTING-THE JOURNAL OF NETWORKS SOFTWARE TOOLS AND APPLICATIONS 2013年第4期16卷 757-763页

作者： Kim, Sang-Hoon Jeong, Young-Sik Hankyong Natl Univ Dept Elect Elect & Control Engn Anseong South Korea Dongkuk Univ Dept Multimedia Engn Seoul South Korea

The intelligent mobile robot with sensors and image processing embedded system combines the suction and aerodynamic attraction to achieve good balance between strong adhesion force and high mobility. Experimental results showed that the robot can move upward on the wall at the speed of 2.9 m/min and carry 5 kg payload in addition to 2.5 kg self-weight, which record the highest payload capacity among climbing robots of similar size. It also implements object detection ability using effective color transform and segmentation technique for the exact target detection on the wall using a embedded camera system, communication module and several active sensors.

关键词： Wall climbing Adhesion force embedded image processing Color segmentation

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FPGA-Based Fast Response image Analysis for Orientational Control in Aerial Manipulation Tasks

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JOURNAL OF SIGNAL processing SYSTEMS FOR SIGNAL image AND VIDEO TECHNOLOGY 2018年第6期90卷 901-911页

作者： Ladig, Robert Leewiwatwong, Suphachart Shimonomura, Kazuhiro Ritsumeikan Univ Dept Robot Kusatsu Shiga 5258577 Japan

In this paper an FPGA-based on-board control system for autonomous orientation of an aerial robot to assist in aerial manipulation tasks is introduced. The system is able to apply yaw control to aid an operator in precisely positioning a drone when it is nearby a bar-like object. This is achieved by applying parallel Hough transform combined with a novel image space separation method, enabling highly reliable results in various circumstances combined with high performance. The feasibility of this approach is shown by applying the system to a multi-rotor aerial robot equipped with an upward directed robotic hand on top of the airframe developed for high altitude manipulation tasks. In order to grasp a bar-like object, the object's orientation is derived from the image data obtained by a monocular camera mounted on the robot. This data is then analyzed by the on-board FPGA system to control yaw angle of the aerial robot. Our experiments show that use of this control system achieves reliable yaw-orientation control.

关键词： FPGA embedded image processing Parallel hough transform Aerial manipulation UAV

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Real-time edge detection and range finding using FPGAs

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OPTIK 2015年第17期126卷 1545-1550页

作者： Khan, Tariq M. Bailey, D. G. Khan, Mohammad A. U. Kong, Yinan Macquarie Univ Dept Engn Sydney NSW 2109 Australia Massey Univ Palmerston North New Zealand Effat Univ Dept Elect & Comp Engn Jeddah Saudi Arabia

The objective of this paper is to design a model which can integrate a range sensor with real time image processing. An FPGA provides physical solutions for most image processing problems and offers a new hardware acceleration opportunity. In this paper we implemented image normalization along with edge detection on real time images and then integrated the range sensor. The model is validated using Spartan-3 FPGA. (C) 2015 Elsevier GmbH. All rights reserved.

关键词： embedded image processing VLSI FPGAs image normalization Edge detection

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Improvements in adhesion force and smart embedded programming of wall inspection robot

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JOURNAL OF SUPERCOMPUTING 2016年第7期72卷 2635-2650页

作者： Kim, SangHoon Choi, Hyun-Ho Yu, YunSeop Hankyong Natl Univ Dept Elect Elect & Control Engn 327 Chungang No Anseong 456749 Gyeonggi Do South Korea Hankyong Natl Univ Inst Informat Technol Convergence 327 Chungang No Anseong 456749 Gyeonggi Do South Korea

An intelligent wall inspection robot with sensors and embedded image processing system was studied based on a combination of vacuum-suction technique and four-wheel drive method to achieve good balance between strong adhesion force and high mobility. To obtain more stable adhesion forces, the height and weight of the robot body were reduced by analyzing the relation between the principal physical input variables and the output performance, such as the suction force and momentum. An object detection system on the embedded programming system for automatic wall inspection was also developed. For successful detection, threshold methods were compared and an improved Otsu method was adopted so that it could handle both unimodal and bimodal distributions well. Through the improvement, the robot could move upward a wall at a speed of 5.3 m/min and carry a payload of at least 7.5 kg in addition to its self-weight and it could also intelligently detect and classify small objects on the wall.

关键词： Wall inspection robot Adhesion force embedded image processing Threshold technology Suction-based method

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A UAV Guidance System Using Crop Row Detection and Line Follower Algorithms

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JOURNAL OF INTELLIGENT & ROBOTIC SYSTEMS 2020年第3-4期97卷 605-621页

作者： Basso, Maik Pignaton de Freitas, Edison Fed Univ Rio Grande Sul UFRGS Elect Engn Grad Program PPGEE Porto Alegre RS Brazil

In precision agriculture, activities such as selective spraying of agrochemicals are essential to maintaining high productivity and quality of agricultural products. The use of unmanned aerial vehicles (UAVs) to perform this activity reduces soil compaction, compared to the use of heavy machinery, and helps to reduce the waste of these artificial substances through a punctual and self-regulating application. This work proposes an entire guiding system for use on UAVs (hardware and software) based on image processing techniques. The software part consists of two algorithms. The first algorithm is the Crop Row Detection which is responsible for the correct identification of the crop rows. The second algorithm is the Line Filter that is responsible for generating the driving parameters sent to the flight controller. In the field experiments performed on the proposed hardware, the algorithm achieved a detection rate of 100% of the crop rows for images with resolutions above 320 x 240. The system performance was measured in laboratory experiments and reached 31.22 FPS for images with small resolution, 320 x 240, and 1.63 FPS for the highest resolution, 1920 x 1080. The main contribution of this work is the design and development of an entire embedded guidance system composed of a hardware and software architectures. Other contributions are: the proposed filter for the image pretreatment;the filter to remove the false positive lines;and the algorithm for generating the guiding parameters based on detected crop rows.

关键词： embedded image processing Autonomous UAV guidance Crop row detection method Precision agriculture application

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A wearable real-time image processor for a vision prosthesis

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COMPUTER METHODS AND PROGRAMS IN BIOMEDICINE 2009年第3期95卷 258-269页

作者： Tsai, D. Morley, J. W. Suaning, G. J. Lovell, N. H. Univ New S Wales Grad Sch Biomed Engn Sydney NSW 2052 Australia Univ Western Sydney Sch Med Sydney NSW 1797 Australia Univ New S Wales Sch Med Sci Sydney NSW 2052 Australia

Rapid progress in recent years has made implantable retinal prostheses a promising therapeutic option in the near future for patients with macular degeneration or retinitis pigmentosa. Yet little work on devices that encode visual images into electrical stimuli have been reported to date. This paper presents a wearable image processor for use as the external module of a vision prosthesis. It is based on a dual-core microprocessor architecture and runs the Linux operating system. A set of image-processing algorithms executes on the digital signal processor of the device, which maybe controlled remotely via a standard desktop computer. The results indicate that a highly flexible and configurable image processor can be built with the dual-core architecture. Depending on the image-processing requirements, general-purpose embedded microprocessors alone may be inadequate for implementing image-processing strategies required by retinal prostheses. Crown Copyright (C) 2009 Published by Elsevier Ireland Ltd. All rights reserved.

关键词： embedded image processing Retinal prosthesis Bionic eye Macular degeneration Retinitis pigmentosa

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Efficient hardware implementation strategy for local normalization of fingerprint images

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JOURNAL OF REAL-TIME image processing 2019年第4期16卷 1263-1275页

作者： Khan, Tariq M. Bailey, Donald G. Khan, Mohammad A. U. Kong, Yinan Macquarie Univ Dept Engn Sydney NSW Australia Massey Univ Sch Engn & Adv Technol Palmerston North New Zealand Effat Univ Biometr & Sensor Lab Jeddah Saudi Arabia

Global techniques do not produce satisfying and definitive results for fingerprint image normalization due to the non-stationary nature of the image contents. Local normalization techniques are employed, which are a better alternative to deal with local image statistics. Conventional local normalization techniques involve pixelwise division by the local variance and thus have the potential to amplify unwanted noise structures, especially in low-activity background regions. To counter the background noise amplification, the research work presented here introduces a correction factor that, once multiplied with the output of the conventional normalization algorithm, will enhance only the feature region of the image while avoiding the background area entirely. In essence, its task is to provide the job of foreground segmentation. A modified local normalization has been proposed along with its efficient hardware structure. On the way to achieve real-time hardware implementation, certain important computationally efficient approximations are deployed. Test results show an improved speed for the hardware architecture while sustaining reasonable enhancement benchmarks.

关键词： embedded image processing FPGA Biometrics

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