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Psychological factors of sports injury caused by wireless communication of embedded microprocessor in social sports teaching and training

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WIRELESS NETWORKS 2023年第3期29卷 1411-1419页

作者： Huang, Changliang Xu, Yuting Sch Shandong Sport Univ Jinan 250102 Shandong Peoples R China Sch Harbin Inst Technol Weihai 264209 Shandong Peoples R China

In the process of physical education and training, students' sports injuries are found, and the laws of injury and psychological factors of injury are discovered from them, to propose targeted preventive measures to reduce the incidence of sports injuries. Based on embedded communication technology, it provides a material means for the sharing of information resources. And the application of the microprocessor makes it very useful in physical education. It is hoped that the incidence of track and field sports injuries of physical education students can be reduced, their potential can be tapped, and their sports life span can be prolonged. This paper establishes the evaluation model of sports injury psychology and emotion, and analyzes the influence of sports injury emotion change on injury rehabilitation and psychological state maintenance cycle in Google data analysis platform. 36 undergraduates from 211 universities were recruited as subjects to show them the introduction information of various sports and ask them to complete the questionnaire. This paper adopts the group design method with psychological quality (high / low) as the independent variable and the choice intention of sports (simple sports / complex sports) as the dependent variable. To select suitable sports for young people to carry out psychological experiments and realize the effective control of scene information. According to the score of psychological quality, the group with high score is regarded as young people with high psychological quality, and the group with low score is regarded as young people with low psychological quality. According to the experimental data, the median score of experiment 1 was 5.00. Those who score higher than 5.0 have high psychological quality, while those who score lower than 5.0 have low learning ability. Taking "psychological quality (high / low) " as the independent variable and "sports project (simple sports / complex sports) choice intention " as the dependent

关键词： Physical education Sports injury Mental state Comprehensive development of body and mind embedded microprocessor Wireless communication

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Factory Test Management System Based on embedded microprocessor

Factory Test Management System Based on Embedded Microproces...

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The 2nd International Conference on Politics, Economics and Law(ICPEL 2017)

作者： Li Tang Baosheng Wang Li He Shuhua ZHANG Department of Information Science and Technology Tianjin University of Finance and Economics Coordinated Innovation Center for Computable Modeling in Management Science Tianjin University of Finance and Economics

The factory test management system is introduced to reduce the failure rate of intelligent *** paper analyzes the structure of foreign factory test management *** on it,this paper introduces the system architecture,testing processes,communications protocols and the software realization of the new factory test management system developed independently,and especially focuses on the design of embedded GUI(Mini GUI) and Linux device *** with the foreign factory test system,this factory test management system with 32-bit microprocessor has the advantage of low-cost,small size and strong flexibility.

关键词： factory test management system embedded microprocessor intelligent instrument Linux device driver

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A 4.5 to 13 Times Energy-Efficient embedded microprocessor with Mainly-Static/Partially-Dynamic Reconfigurable Array Accelerator 10

A 4.5 to 13 Times Energy-Efficient Embedded Microprocessor w...

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IEEE Asian Solid-State Circuits Conference (A-SSCC)

作者： Hida, Itaru Kim, Dahoo Asai, Tetsuya Motomura, Masato Hokkaido Univ Grad Sch Informat Sci & Technol Sapporo Hokkaido Japan

ISBN: (纸本)9781479940899

Conventional processors are energy in-efficient in that they fail to utilize the fact that most of their time and energy are spent on heavily-recursively executed small code segments. A DYNaSTA accelerator, proposed and implemented, is an architectural solution to such a problem. It is an reconfigurable array accelerator featuring an hybrid architecture: only a limited portion is reconfigured dynamically (i.e., frequently) while the rest is reconfigured statically (i.e., only occasionally). This way, the DYNaSTA accelerator tries to achieve both exibility and energy-efficiency at the same time. Results of power simulation and fabricated chip measurements have been quite encouraging: 4.5 to 13 times energy efficiency will be made possible by this accelerator when compared with a conventional embedded microprocessor.

关键词： microprocessor chips reconfigurable architectures DYNaSTA accelerator energy-efficient embedded microprocessor fabricated chip measurements heavily-recursively executed small code segments hybrid architecture mainly-static-partially-dynamic reconfigurable array accelerator Arrays Clocks Frequency measurement Power demand Power measurement Registers Semiconductor device measurement composite structures semiconductor device measurement frequency measurement Power measurement Reconfigurable architectures microprocessor chips Power demand Registers Timing devices Energy efficiency embedded microprocessor arrays

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TransFusionNet: Semantic and Spatial Features Fusion Framework for Liver Tumor and Vessel Segmentation Under JetsonTX2

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IEEE JOURNAL OF BIOMEDICAL AND HEALTH INFORMATICS 2023年第3期27卷 1173-1184页

作者： Wang, Xun Zhang, Xudong Wang, Gan Zhang, Ying Shi, Xin Dai, Huanhuan Liu, Min Wang, Zixuan Meng, Xiangyu China Univ Petr Dept Comp Sci & technol Qingdao 266580 Shandong Peoples R China Univ Chinese Acad Sci High Performance Comp Res Ctr Beijing 100190 Peoples R China Qingdao Univ Sci & Technol Sch Math & Phys Qingdao 266061 Shandong Peoples R China Qingdao Municipal Hosp Minimally Invas Intervent Therapy Ctr Qingdao 266011 Shandong Peoples R China

Liver cancer is one of the most common malignant diseases worldwide. Segmentation and reconstruction of liver tumors and vessels in CT images can provide convenience for physicians in preoperative planning and surgical intervention. In this paper, we introduced a TransFusionNet framework, which consists of a semantic feature extraction module, a local spatial feature extraction module, an edge feature extraction module, and a multi-scale feature fusion module to achieve fine-grained segmentation of liver tumors and vessels. In addition, we applied the transfer learning approach to pre-train using public datasets and then fine-tune the model to further improve the fitting effect. Furthermore, we proposed an intelligent quantization scheme to compress the model weights and achieved high performance inference on JetsonTX2. The TransFusionNet framework achieved mean IoU of 0.854 in vessel segmentation task, and achieved mean IoU of 0.927 in liver tumor segmentation task. When profiling the Computational Performance of the quantized inference, our quantized model achieved 4TFLOPs on Node with NVIDIA RTX3090 and 132GFLOPs on JetsonTX2. This unprecedented segmentation effect solves the accuracy and performance bottleneck of automated segmentation to a certain extent.

关键词： Feature extraction Liver Tumors Image segmentation Computed tomography Computational modeling Transformers Liver tumor liver vessel medical image segmentation transformer 3D reconstruction embedded microprocessor computer-aided diagnosis

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An infrasound source localisation algorithm for improving location accuracy of gas pipeline leakage detection system

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INTERNATIONAL JOURNAL OF embedded SYSTEMS 2022年第1期15卷 9-18页

作者： Zhang, Mei Gao, Li Zhang, Xiao Zhang, Shuangshuang Anhui Univ Sci & Technol Sch Elect & Informat Engn Huainan Peoples R China

To solve inaccurate location for urban gas pipeline leakage, an optimised algorithm based on infrasound source location is developed in this study. First, wavelet transform is adopted to denoise the infrasound signal that is collected from gas pipeline leakage by the sensor array. Subsequently, the generalised cross-correlation method is proposed to determine the delay between adjacent sensor nodes. Next, the location of the leakage point is calculated using the built location model of leakage source. A gas pipeline leakage detection system is developed using low-power WAN technology and embedded microprocessor to implement this localisation algorithm. Lastly a simulation experiment of leakage location is performed in the laboratory. As revealed from the experimental results, the detection system exhibits high location accuracy.

关键词： gas pipeline leakage detection system localisation algorithm infrasound source generalised cross-correlation method embedded microprocessor

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Advanced System-on-Chip Field-Programmable-Gate-Array-Powered Data Acquisition System for Pixel Detectors

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SENSORS 2024年第1期24卷 218页

作者： Jimenez-Sanchez, Jorge Blanco-Carmona, Pedro Hinojo-Montero, Jose Maria Palomo, Francisco Rogelio Millan, Rafael Luis Munoz-Chavero, Fernando Univ Seville Dept Elect Engn Seville 41092 Spain

Particle detector systems require data acquisition systems (DAQs) as their back-end. This paper presents a new edge-computing DAQ that is capable of handling multiple pixel detectors simultaneously and was designed for particle-tracking experiments. The system was designed for the ROC4SENS readout chip, but its control logic can be adapted for other pixel detectors. The DAQ was based on a system-on-chip FPGA (SoC FPGA), which includes an embedded microprocessor running a fully functional Linux system. An application using a client-server architecture was developed to facilitate remote control and data visualization. The comprehensive DAQ is very compact, thus reducing the typical hardware load in particle tracking experiments, especially during the obligatory characterization of particle telescopes.

关键词： data acquisition systems edge computing pixel detectors particle tracking hybrid pixel read-out chip system-on-chip FPGA embedded microprocessor telescope

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Functional Verification Flow for an embedded microprocessor

Functional Verification Flow for an Embedded Microprocessor

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International Conference on Industrial Control and Electronics Engineering (ICICEE)

作者： Wang, Danghui He, Hua Northwestern Polytech Univ Sch Comp Sci & Technol Xian 710072 Peoples R China

ISBN: (纸本)9780769547923

Design verification is the process of determining that a design accurately represents the developer's conceptual description and specifications. These days, design verification represents bring about 60% of total cost of the development of microprocessors or microprocessor cores. A huge number of different activities performed in different stages of the design flow and at different levels of abstraction. Based on the analysis of the structure of an embedded microprocessor, this paper shows the hierarchical verification flow for the microprocessor. The verification flow integrates several verification methods such as coding style checking, register transfer level simulation based on module, system level simulation, virtual machine based verification, timing verification and FPGA based verification. The embedded microprocessor has been successfully fabricated on the SIMC 0.18 mu m COMS technology.

关键词： Verification Flow Hierarchical embedded microprocessor

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Small Private Key MQPKS on an embedded microprocessorg

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SENSORS 2014年第3期14卷 5441-5458页

作者： Seo, Hwajeong Kim, Jihyun Choi, Jongseok Park, Taehwan Liu, Zhe Kim, Howon Pusan Natl Univ Pusan 609735 South Korea Univ Luxembourg Lab Algorithm Cryptol & Secur L-1359 Luxembourg Luxembourg

Multivariate quadratic (M Q) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to M Q cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and embedded Systems, 2011), a small public key M Q scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key M Q scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing M Q on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key M Q scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

关键词： public key cryptography small private key multivariate quadratic cryptography embedded microprocessor efficient software implementation ATxmega128a1 AES accelerator random number generator signature generation

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Karatsuba-Block-Comb technique for elliptic curve cryptography over binary fields

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SECURITY AND COMMUNICATION NETWORKS 2015年第17期8卷 3121-3130页

作者： Seo, Hwajeong Liu, Zhe Choi, Jongseok Kim, Howon Pusan Natl Univ Comp Engn Pusan 609735 South Korea Univ Luxembourg Lab Algorithm Cryptol & Secur L-1359 Luxembourg Luxembourg

Efficient implementation of elliptic curve cryptography on resource-constrained microcontroller is considered to be one of the hot and challenging research topics because of the limited computing power and storages of target platforms and high computational costs of elliptic curve cryptography. In this paper, we focus on enhancing the performance of scalar multiplication over GF(2(m)) by suggesting a new technique for speeding up the performance of multiplication, called Karatsuba-Block-Comb (KBC) multiplication. KBC method combines both the advantages of Karatsuba algorithm and Block-Comb method. This technique replaces the part of expensive Block-Comb binary field multiplications with several cheap additions by following Karatsuba rule. In case of squaring, we describe an optimized squaring algorithm with 8-bit look-up table that is significantly faster than previous works with 4-bit look-up table. Both of the proposed approaches improve the best known results by a factor of 24.6% and 16.8% (160-bit operand) over 8-bit AVR processor (Atmel Corporation, San Jose, CA, USA), respectively. Finally, we realize the scalar multiplication over GF(2(163)), which only requires 0.29s for a full scalar multiplication when the processor runs at 7.37MHz. This result outperforms the previous best implementation by a factor of 9.3%. The research results presented in this paper prove that it is also possible to achieve high performance over binary fields by combing the algorithm with sub-quadratic complexity. Furthermore, we suggest constant time KBC method. Block-Comb method does not provide constant time, and look-up table method is also vulnerable to memory address side channel attack. However, our method is establishing the scalar multiplication in 0.35s with high security against both attacks. Copyright (c) 2015 John Wiley & Sons, Ltd.

关键词： public-key cryptography elliptic curve cryptography embedded microprocessor binary field multiplication

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Internet of things (IoT): Technologies and applications

Internet of things (IoT): Technologies and applications

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International Conference on Advances in ICT for Emerging Regions

作者： Simon Jiang Andes Technology Corporation Taiwan

All of the analysis report pointed out the total connected things will reach 50 billion in 2020. So the internet of things (IoT) is major and big market for semiconductor and IC design. IoT is a big trend and there are many opportunities to create a new product, project and research. I talk about the emerging technology in IoT and wearable device market. One important of challenge is low power. Therefore, the power efficiency is the new battleground in IoT. And then, one of another important is security function. So choose an embedded microprocessor is very important for IoT or wearable device. I give a brief description of Andes CPU and it is suitable in IoT solution. Finally, Andes CPU has successful in IoT and wearable device market, a lot of products were made by IoT companies from Andes CPU licensed and these products will be displayed, especially in mobile and communication applications.

关键词： Internet of things Wearable Andes embedded microprocessor central processing units COMMUNICATIONS APPLICATION Internets dynamic efficiency

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