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Profiling soft-core processor applications for hardware/software partitioning

JOURNAL OF SYSTEMS ARCHITECTURE 2005年第5期51卷 315-329页

作者： Finc, A Zemva, A Univ Ljubljana Fac Elect Engn Lab Integrated Circuits Design Ljubljana Slovenia

In this paper, we present an efficient approach to HW/SW partitioning of applications targeted for embedded soft-core SoPC and programmable logic. The methodology is based on the iterative performance analysis of the initial functional SW description and performance estimation of various HW/SW partitioning configurations. The main focus is on adequate profiling of arbitrary SW code regions (function or single instruction level) with clock-cycle accuracy without introducing additional execution overhead. In order to support the profiling for partitioning, we have developed the COMET Profiler tool. The performance analysis and estimation in the simulation and implementation domains are supported, necessitating no design and implementation of HW co-processing blocks for the partitioning evaluation. The design process is illustrated with two case studies. (c) 2004 Elsevier B.V. All rights reserved.

关键词： hardwarelsoftware co-design HW/SW partitioning field programmable gate array embedded soft-core processor performance analysis profiling system-on-programmable-chip (SoPC)

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A systematic approach to profiling for hardware/software partitioning

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COMPUTERS & ELECTRICAL ENGINEERING 2005年第2期31卷 93-111页

作者： Finc, M Zemva, A Univ Ljubljana Fac Elect Engn Lab Integrated Circuits Design Ljubljana 1000 Slovenia

In this paper, we present an efficient approach to profiling for HW/SW partitioning. The execution of arbitrary SW code regions is analyzed with a clock-cycle accuracy without introducing an additional profiling induced performance overhead. Based on the profiling principle, performance analysis of the initial functional SW description and performance estimation of various HW/SW partitioning configurations are systematically and iteratively carried out. For an efficient evaluation of different partitioning possibilities no design and implementation of HW co-processing blocks are necessary. The principle equally covers the simulation and implementation domains. The approach is highly suitable for embedded soft-core SoPC applications. In order to demonstrate its use, we developed a COMET Profiler tool. The design flow is illustrated with two case studies. (c) 2005 Elsevier Ltd. All rights reserved.

关键词： hardware/software (HW/SW) co-design HW/SW partitioning Field Programmable gate array (FPGA) embedded soft-core processor performance analysis profiling system-on-programmable-chip (SoPC)

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