A very fast and low-power address bus encoder, whose critical path delay and area are only weakly dependent on the address bus width, is presented. Although the encoding algorithm of the proposed structure is the same...
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A very fast and low-power address bus encoder, whose critical path delay and area are only weakly dependent on the address bus width, is presented. Although the encoding algorithm of the proposed structure is the same as the INC-XOR encoding, its encoder and decoder architectures, called DX, are much faster. The DX architecture implements the INC-XOR encoding partially (partial DX architecture) or fully (registered DX architecture). The partial implementation, which is faster and consumes less power and silicon area, is appropriate for cases where the size of the basic block (sequential addresses without branches or jumps) is bounded, for example, by 256. The registered DX architecture uses a multi-stage pipelined structure with pseudo-incrementers to reduce the combinational delay of each pipeline stage. The two DX implementations (partial and registered) are compared with three conventional implementations of INC-XOR realised using the ripple carry, the carry look-ahead and Sklansky prefix incrementers. The results of the critical path delay, gate count, power-delay product and energy-delay product show considerable improvements over the conventional implementations.
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