This study proposes a dynamic bit-level encoding algorithm (DEA) and introduces the S+DEA compression framework, which enhances compression efficiency by integrating the DEA with image segmentation as a preprocessing ...
详细信息
This study proposes a dynamic bit-level encoding algorithm (DEA) and introduces the S+DEA compression framework, which enhances compression efficiency by integrating the DEA with image segmentation as a preprocessing step. The novel approaches were validated on four different datasets, demonstrating strong performance and broad applicability. A dedicated data structure was developed to facilitate lossless storage and precise reconstruction of compressed data, ensuring data integrity throughout the process. The evaluation results showed that the DEA outperformed all benchmark encoding algorithms, achieving an improvement percentage (IP) value of 45.12, indicating its effectiveness as a highly efficient encoding method. Moreover, the S+DEA compression algorithm demonstrated significant improvements in compression efficiency. It consistently outperformed BPG, JPEG-LS, and JPEG2000 across three datasets. While it performed slightly worse than JPEG-LS in medical images, it remained competitive overall. A dataset-specific analysis revealed that in medical images, the S+DEA performed close to the DEA, suggesting that segmentation alone does not enhance compression in this domain. This emphasizes the importance of exploring alternative preprocessing techniques to enhance the DEA's performance in medical imaging applications. The experimental results demonstrate that the DEA and S+DEA offer competitive encoding and compression capabilities, making them promising alternatives to existing frameworks.
Maximum run-length limited codes are constraint codes used in communication and data storage systems. Insertion/deletion correcting codes correct insertion or deletion errors caused in transmitted sequences and are us...
详细信息
Maximum run-length limited codes are constraint codes used in communication and data storage systems. Insertion/deletion correcting codes correct insertion or deletion errors caused in transmitted sequences and are used for combating synchronization errors. This paper investigates the maximum run-length limited single insertion/deletion correcting (RLL-SIDC) codes. More precisely, we construct efficiently encodable and decodable RLL-SIDC codes. Moreover, we present its encoding and decoding algorithms and show the redundancy of the code.
In this paper, an algorithm for quasi-cyclic low-density parity-check code (QC-LDPC) encoding is proposed. The correctness of the algorithm is validated on the FPGA evaluation board. Experimental results show that the...
详细信息
ISBN:
(纸本)9781665481557
In this paper, an algorithm for quasi-cyclic low-density parity-check code (QC-LDPC) encoding is proposed. The correctness of the algorithm is validated on the FPGA evaluation board. Experimental results show that the encoding delay can be reduced by 3.3 times compared to the conventional encoding algorithm based on generator matrix. In addition, the algorithm also reduces the complexity of hardware implementation.
Many different encoding algorithms for systematic polar codes (SPC) have been introduced since SPC was proposed in 2011. However, the number of the computing units of exclusive OR (XOR) has not been optimized yet. Acc...
详细信息
Many different encoding algorithms for systematic polar codes (SPC) have been introduced since SPC was proposed in 2011. However, the number of the computing units of exclusive OR (XOR) has not been optimized yet. According to an iterative property of the generator matrix and particular lower triangular structure of the matrix, we propose an optimized encoding algorithm (OEA) of SPC that can reduce the number of XOR computing units compared with existing non-recursive algorithms. We also prove that this property of the generator matrix could extend to different code lengths and rates of the polar codes. Through the matrix segmentation and transformation, we obtain a submatrix with all zero elements to save computation resources. The proportion of zero elements in the matrix can reach up to 58.5% from the OEA for SPC when the code length and code rate are 2048 and 0.5, respectively. Furthermore, the proposed OEA is beneficial to hardware implementation compared with the existing recursive algorithms in which signals are transmitted bidirectionally.
In the world of big data there has been a steady shift from parallel to high speed serial digital communication buses which requires devices with much higher data throughput. Serializing the data and sending at a fast...
详细信息
ISBN:
(纸本)9781538695333
In the world of big data there has been a steady shift from parallel to high speed serial digital communication buses which requires devices with much higher data throughput. Serializing the data and sending at a faster rate, reduces the pin counts which in turn lead to much smaller devices in an integrated circuit compared to parallel communication. Line coding can potentially help in high data transfers. In this paper 128b/130b line coding algorithm has been proposed which has the double the payload of conventional 64b/66b encoding technique, with same number of preamble bits. This increases the data transfer rate drastically. The polynomial for the scrambler has been used from IEEE clause. The proposed 128b/130b encoding algorithm has been coded using Verilog and simulated using Quartus II 9.0v. The parameters such as Setup time, Hold time, Maximum frequency, power and slack for 8b/10b, 64b/66b and 128b/130b has been compared and tabulated. The layout has been designed for 128b/130b using Cadence Encounter 14.26 tool. The comparison shows that proposed algorithm has higher data rate at the expense of increase in hardware utilization.
In this paper, a 1-GS/s 12-bit pipelined folding analog-to-digital converter (ADC) fabricated in 40 nm CMOS technology is presented. A new encoding algorithm based on distributed quantization is proposed to simplify t...
详细信息
In this paper, a 1-GS/s 12-bit pipelined folding analog-to-digital converter (ADC) fabricated in 40 nm CMOS technology is presented. A new encoding algorithm based on distributed quantization is proposed to simplify the quantization process of the structure with odd folding factor and reduce the hardware consumption of the circuit. The ADC achieves spurious free dynamic range (SFDR) > 72 dB and signal-to-noise and distortion ratio (SNDR) > 57 dB in low input frequencies.
The transportation network of the city is dynamic and stochastic, The problem of dynamic stochastic shortest path is NP-hard. the optimal problem of path is widely used in the fields of transportation, communication a...
详细信息
ISBN:
(纸本)9781728101699
The transportation network of the city is dynamic and stochastic, The problem of dynamic stochastic shortest path is NP-hard. the optimal problem of path is widely used in the fields of transportation, communication and computer network An improved self adaptive genetic algorithm is proposed by encoding the chromosomal *** paper investigates the shortest path problem based on the genetic algorithm principle, and improved genetic algorithm by adjusting the encoding parameters. Mny experiments indicate that the improved genetic algorithm could adapt to new transportation rapidly in global optimization than A* algorithm and Dijkstra algorithm and obtain the better solutions in the shortest path problem in the fields of transportation and computer network
Grid codes are an important part of a grid system and provide a unique identifier for the cells in the spherical triangular discrete global grid, where the transformation between geographic coordinates and grid codes ...
详细信息
Grid codes are an important part of a grid system and provide a unique identifier for the cells in the spherical triangular discrete global grid, where the transformation between geographic coordinates and grid codes is the basis of global spatial data integration and various analytical applications. Owing to the particularity of the topological properties, the spherical space cannot be continuously paved with the same grid cells as those in the plane space. Thus, the recursive approximation method is typically used to establish the transformation algorithm between the geographic coordinates and the grid codes. The efficiency of those algorithms that were based on recursive approximation obviously decreased with the increased grid subdivision level;thus, it is not conducive to the integration of massive high-resolution spatial data. Whereas the geometric properties of the grid cells in the spherical triangular discrete global grid differ during the initial subdivision levels, as the level increases, these geometric properties tend to be the same, along with the properties of the local regions similar to the plane. Considering this characteristic, this paper proposes a hybrid bidirectional transformation algorithm. In the proposed algorithm, the recursive approximation method is used at the lower level where there is a large difference in the geometrical properties of the grid cells, and the direct mapping method using a similar plane grid is used at the higher level where the geometrical properties of the grid cells are virtually the same. In experiments conducted using the proposed algorithm with geographic coordinates at different scales and grid codes at different levels, the running time remained stable with no significant change throughout increases in the hierarchical level. Further, it was proven to satisfy the requirements of the absolute accuracy evaluation method. Compared with the traditional recursive approximation algorithm, the proposed algorithm has o
Arikan has shown that systematic polar codes (SPC) outperform non-SPC (NSPC). However, the performance gain comes at the price of elevated encoding complexity, i.e., compared with NSPC, the available encoding methods ...
详细信息
Arikan has shown that systematic polar codes (SPC) outperform non-SPC (NSPC). However, the performance gain comes at the price of elevated encoding complexity, i.e., compared with NSPC, the available encoding methods for SPC require higher memory and computation. In this letter, we propose an efficient encoding algorithm requiring only N bits of memory and having (N/2) log(2) N XOR operations. Moreover, the auxiliary variables in the algorithm can share the memory to reduce extra memory requirement. Furthermore, a parallel 2-bit encoding algorithm is also presented to improve the encoding throughput. Remarkably, we show that parallel encoding can be implemented with the same number of XOR operations and memory bits. Finally, the proposed encoding algorithm can be directly used for NSPC with the same complexity.
Based on 512-bit SIMD instructions, a Huffman encoding implementation, termed Huffman-SIMD, is proposed. The proposed implementation consists of four parts: establishing the Huffman coding table, data initialization, ...
详细信息
Based on 512-bit SIMD instructions, a Huffman encoding implementation, termed Huffman-SIMD, is proposed. The proposed implementation consists of four parts: establishing the Huffman coding table, data initialization, look-up table, and shifting and merging data. We establish the code table according to the characteristics of SIMD instructions. The code table is divided into eight sub-tables, with every two sub-tables in a group. It uses flag bits in each storage item to distinguish codewords from non-codewords, so the code table does not need to store the length of codewords in order to reduce the use of registers. After accelerating the table lookup operation using SIMD instruction, the valid size in each entry is different. Therefore, the shift merging algorithm is designed to operate on data and eliminate the spacing between data. This paper uses three datasets, Calgary, Silesia and Canterbury, to evaluate the implementation and compare it with the existing Huff0 library. The throughput is improved by 12.01% on average. Thus the implementation proposed in this paper improves the coding efficiency.
暂无评论