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Bitstream decoding processor for fast entropy decoding of variable length coding-based multiformat videos

OPTICAL ENGINEERING 2014年第6期53卷

作者： Jo, Hyunho Sim, Donggyu Kwangwoon Univ Dept Comp Engn Seoul 139701 South Korea

We present a bitstream decoding processor for entropy decoding of variable length coding-based multiformat videos. Since most of the computational complexity of entropy decoders comes from bitstream accesses and table look-up process, the developed bitstream processing unit (BsPU) has several designated instructions to access bitstreams and to minimize branch operations in the table look-up process. In addition, the instruction for bitstream access has the capability to remove emulation prevention bytes (EPBs) of H. 264/AVC without initial delay, repeated memory accesses, and additional buffer. Experimental results show that the proposed method for EPB removal achieves a speed-up of 1.23 times compared to the conventional EPB removal method. In addition, the BsPU achieves speed-ups of 5.6 and 3.5 times in entropy decoding of H. 264/AVC and MPEG-4 Visual bitstreams, respectively, compared to an existing processor without designated instructions and a new table mapping algorithm. The BsPU is implemented on a Xilinx Virtex5 LX330 field-programmable gate array. The MPEG-4 Visual (ASP, Level 5) and H. 264/AVC (Main Profile, Level 4) are processed using the developed BsPU with a core clock speed of under 250 MHz in real time. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： entropy decoding emulation prevention byte H. 264/AVC multiformat videos

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JParEnt: Parallel entropy decoding for JPEG decompression on heterogeneous multicore architectures 7

JParEnt: Parallel entropy decoding for JPEG decompression on...

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Euro-Par Conference / 7th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM) held in conjunction with the 21st SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Sodsong, Wasuwee Jung, Minyoung Park, Jinwoo Burgstaller, Bernd Yonsei Univ Dept Comp Sci Seoul South Korea

ISBN: (纸本)9781450341967

The JPEG format employs Huffman codes to compress the entropy data of an image. Huffman codewords are of variable length, which makes parallel entropy decoding a difficult problem. To determine the start position of a codeword in the bitstream, the previous codeword must be decoded first. We present JParEnt, a new approach to parallel entropy decoding for JPEG decompression on heterogeneous multicores. JParEnt conducts JPEG decompression in two steps: (1)an efficient sequential scan of the entropy data on the CPU to determine the start-positions (boundaries) of coefficient blocks in the bitstream, followed by (2)a parallel entropy decoding step on the graphics processing unit (GPU). The block boundary scan constitutes a reinterpretation of the Huffman-coded entropy data to determine codeword boundaries in the bitstream. We introduce a dynamic workload partitioning scheme to account for GPUs of low compute power relative to the CPU. This configuration has become common with the advent of SoCs with integrated graphics processors (IGPs). We leverage additional parallelism through pipelined execution across CPU and GPU. For systems providing a unified address space between CPU and GPU, we employ zero-copy to completely eliminate the data transfer overhead. Our experimental evaluation of JParEnt was conducted on six heterogeneous multicore systems: one server and two desktops with dedicated GPUs, one desktop with an IGP, and two embedded systems. For a selection of more than 1000JPEG images, JParEnt outperforms the SIMD-implementation of the libjpeg-turbo library by up to a factor of 4.3x, and the previously fastest JPEG decompression method for heterogeneous multicores by up to a factor of 2.2x. JParEnt's entropy data scan consumes 45% of the entropy decoding time of libjpeg-turbo on average. Given this new ratio for the sequential part of JPEG decompression, JParEnt achieves up to97% of the maximum attainable speedup (95% on average). On the IGP-based desktop platform,

关键词： JPEG decoding entropy decoding prefix codes heterogeneous multicores GPU programming

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Hardware architecture design of HEVC entropy decoding 19

Hardware architecture design of HEVC entropy decoding

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19th IEEE International Symposium on Parallel and Distributed Processing with Applications (IEEE ISPA)

作者： Wang, Shiyu Zhang, Shengbing Wang, Jihe Chang, Libo Feng, Liangyou Fan, Xiaoya Northwestern Polytech Univ Sch Comp Sci Xian Peoples R China Minist Educ Engn Res Ctr Embedded Syst Integrat Xian Peoples R China Northwestern Polytech Univ Natl Engn Lab Integrated AeroSp Ground Ocean Big Xian Peoples R China

ISBN: (纸本)9781665435741

As the latest generation of digital video coding standard, HEVC has technically optimized multiple modules such as related frame prediction, block processing and entropy coding in the frequency coding and decoding framework. However, flexible and efficient coding algorithms make the amount of calculation in the video decoding and reconstruction process increase dramatically. The energy efficiency of traditional processors is limited, and the decoding calculation process is difficult to meet the current needs of ultra-highdefinition video playback. For the most important and timeconsuming bitstream analysis and entropy decoding part of the HEVC decoding process, a new hardware architecture strategy is provided, which can effectively improve the HEVC decoding performance. In this paper, the designed data access module, bitstream analysis and entropy decoding unit are simulated and verified. Build an FPGA verification platform, and use the main tier standard test sequence to simulate and verify the designed hardware acceleration architecture. The experimental results show that the hardware architecture of bitstream analysis and entropy decoding designed in this paper can reach the functions and performance indicators specified by the HEVC standard Level-4 main tier, and the bitstream analysis acceleration effect is good. This thesis aims at the current HEVC decoding calculation characteristics, and through the design of hardware architecture verification, it provides new solutions and hardware architecture ideas for subsequent HEVC encoding and decoding performance optimization.

关键词： HEVC FPGA bitstream entropy decoding video compression

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An improved implementation scheme for AVS entropy decoding based on FPGA

An improved implementation scheme for AVS entropy decoding b...

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2010 International Conference on Remote Sensing (ICRS 2010)

作者： WEN-GE ZHU, QING-MING YI, WEI-DAN LI College of Information Science and Technology Actions-Jinan University Integrated Circuit Design Joint Laboratory Guangzhou, China

An improved implementation scheme for AVS entropy decoding based on FPGA is proposed in this paper. The additional control circuit is used to get rid of the code streams parsed every cycle without adding any parsing periods. And it makes the barrel shifter prepositive so as to balance the time sequence path in the front end. In this way, the deficiency in the traditional structure of variable length decoding is conquered. Compared with the traditional structure, the proposed scheme achieves 43.2 percent time sequence improvement at the cost of 2.5 percent LE and the real-time high-definition (4:2:2) video decoding sequence can be implemented on Cyclone II EP2C35F672C6.

关键词： AVS entropy decoding barrel shifter FPGA

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An Improved Implementation Scheme for AVS entropy decoding Based on FPGA

An Improved Implementation Scheme for AVS Entropy Decoding B...

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2011 International Conference on Informatics,Cybernetics,and Computer Engineering(ICCE 2011)

作者： Wen-Ge Zhu Qing-Ming Yi Wei-Dan Li College of Information Science and Technology Actions-Jinan University Integrated Circuit Design Joint Laboratory

An improved implementation scheme for AVS entropy decoding based on FPGA is proposed in this *** additional control circuit is used to get rid of the code streams parsed every cycle without adding any parsing *** it makes the barrel shifter prepositive so as to balance the time sequence path in the front *** this way,the deficiency in the traditional structure of variable length decoding is *** with the traditional structure,the proposed scheme achieves 43.2 percent time sequence improvement at the cost of 2.5 percent LE and the real-time high-definition(4:2:2) video decoding sequence can be implemented on Cyclone II EP2C35F672C6.

关键词： AVS entropy decoding barrel shifter FPGA

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JParEnt: Parallel entropy decoding for JPEG decompression on heterogeneous multicore architectures

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2017年第15期29卷

作者： Sodsong, Wasuwee Jung, Minyoung Park, Jinwoo Burgstaller, Bernd Yonsei Univ Dept Comp Sci Seoul South Korea

关键词： JPEG decoding entropy decoding prefix codes heterogeneous multicores GPU programming

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New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC decoding

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2010年第7期20卷 1007-1017页

作者： Lee, Jun-Young Lee, Jae-Jin Park, SeongMo Elect & Telecommun Res Inst Multimedia Processor Res Team Taejon 305700 South Korea Univ Sci & Technol Dept Comp Software Engn Taejon 305333 South Korea

In this paper, new codeword structures, tables, and searching methods for fast and efficient coeff_token, total_zeros, and run_before decoding are developed. This new achievement is mainly based on the fact that the context-adaptive variable length coding (CAVLC) decoding can be modeled as a finite state machine. In order to quantitatively evaluate the proposed method in terms of decoding speed and complexity, we define the iteration bound (1/(tau) over tilde) and the complexity ratio (CR). Using these gauge variables, we show that the new algorithms reduce (tau) over tilde to about one third and complexity ratio to 0.95. This means that the proposed techniques reduce the decoding time to about one third and memory access count by 90% compared to those of the conventional methods without implementation overheads. Multiple-symbol parallel decoding method for run_before syntax element is proposed based on a bit-positioning with the critical path latency of only one multiplexer for the post-combination process. The proposed methods make it possible to implement a fast and efficient CAVLC decoding without losing video quality on any environments.

关键词： Context-adaptive variable length coding (CAVLC)/decoding entropy decoding H.264/advanced video coding (AVC)

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A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2012年第2期22卷 272-281页

作者： Liao, Yuan-Hsin Li, Gwo-Long Chang, Tian-Sheuan PixArt Imagine Inc Hsinchu 300 Taiwan Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan

In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.

关键词： Binary arithmetic coding CABAC entropy decoding H.264/AVC syntax parsing

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Fast CAVLD of H.264/AVC on bitstream decoding processor

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EURASIP JOURNAL ON IMAGE AND VIDEO PROCESSING 2013年第1期2013卷 1-14页

作者： Seo, Jung-Han Jo, Hyun-Ho Sim, Dong-Gyu Kim, Doo-Hyun Song, Joon-Ho Kwangwoon Univ Dept Comp Engn Seoul 139701 South Korea Samsung Adv Inst Technol Yongin 446712 Gyeonggi Do South Korea

This paper presents a fast context-based adaptive variable-length decoding (CAVLD) method of H.264/AVC with a very long instruction word-based bitstream processing unit (BsPU) designed for entropy decoding of multiple video formats. A new table mapping algorithm for the coeff_token, level, and run_before syntax elements of the quantized transform coefficients is proposed, and many branch operations are removed by utilizing several designated instructions in the BsPU. By applying designated instructions and the proposed table mapping algorithm to CAVLD, we found that the proposed fast CAVLD method achieves an increase of approximately 47% in the decoding speed and a reduction of approximately 59% in memory requirements for the table mapping.

关键词： CAVLD H.264/AVC entropy decoding Video compression

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Efficient FPGA Implementation of H.264 CAVLC entropy Decoder

Efficient FPGA Implementation of H.264 CAVLC Entropy Decoder

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8th IEEE International Design and Test Symposium (IDT)

作者： Siblini, Ali Baaklini, Elias Sbeity, Hassan Fadlallah, Ahmad Niar, Smail Lebanese Univ Beirut Lebanon Arab Open Univ Beirut Lebanon Univ Valenciennes Valenciennes France

ISBN: (纸本)9781479935253

Multiprocessor-system-on-a-chip (MPSoC) is the dominating architecture in embedded systems. Applications need to be multi-threaded to benefit from the concurrency provided by the MPSoC. Many parallel versions of the new emerging H.264/AVC [I] already exist. However, providing a full parallel H.264 version is blocked by the fact that all parts of the decoder depend on the first sequential stage of the decoding process which is the entropy decoder (mainly CAVLC). The entropy decoder consumes about 30% [8] of the total time of the decoder. In this work, we propose an optimized FPGA design achieving the demands of multi-threaded H.264 decoder versions which can be integrated in an MPSoC. We focus in our work on time optimization and on cycle number decrease when decoding an encoded 4x4 block of pixels. We also aim to achieve a design that operates at high frequencies. The work leads to the ability to decode at least 62 frames per second for LID resolution 1280x720. decoding takes 22 clock cycles for one block of 4x4 pixels at most. The design has an upper frequency limit of 247MHz. High resolutions frames such as 1920x1088 FHD (full high definition) video maintain a minimum frequency of 30 fps.

关键词： FPGA CALVC entropy decoding H.264 Video Decodin Multi-Core Embedded Systems

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