error codes induced by M-ary modulation and modulation selection in network-based control systems are *** is the first time the issue of error codes induced by M-ary modulation is addressed in control *** network-base...
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error codes induced by M-ary modulation and modulation selection in network-based control systems are *** is the first time the issue of error codes induced by M-ary modulation is addressed in control *** network-based control systems,error codes induced by noisy channel can significantly decrease the quality of *** solve this problem,the network-based control system with delay and noisy channel is firstly modeled as an asynchronous dynamic system(ADS).Secondly,conditions of packet with error codes(PEC)loss rate by using M-ary modulation are obtained based on dynamic output feedback ***,more importantly,the selection principle of M-ary modulation is proposed according to the measured signal-to-noise ratio(SNR)and conditions of PEC loss ***,system stability is analyzed and controller is designed through Lyapunov function and linear matrix inequality(LMI)scheme,and numerical simulations are made to demonstrate the effectiveness of the proposed scheme.
Operating system kernels carry a large number of security checks to validate security-sensitive variables and operations. For example, a security check should be embedded in a code to ensure that a user-supplied point...
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ISBN:
(纸本)9781450356930
Operating system kernels carry a large number of security checks to validate security-sensitive variables and operations. For example, a security check should be embedded in a code to ensure that a user-supplied pointer does not point to the kernel space. Using security-checked variables is typically safe. However, in reality, security-checked variables are often subject to modification after the check. If a recheck is lacking after a modification, security issues may arise, e.g., adversaries can control the checked variable to launch critical attacks such as out-of-bound memory access or privilege escalation. We call such cases lacking-recheck (LRC) bugs, a subclass of TOCTTOU bugs, which have not been explored yet. In this paper, we present the first in-depth study of LRC bugs and develop LRSan, a static analysis system that systematically detects LRC bugs in OS kernels. Using an inter-procedural analysis and multiple new techniques, LRSan first automatically identifies security checks, critical variables, and uses of the checked variables, and then reasons about whether a modification is present after a security check. A case in which a modification is present but a recheck is lacking is an LRC bug. We apply LRSan to the latest Linux kernel and evaluate the effectiveness of LRSan. LRSan reports thousands of potential LRC cases, and we have confirmed 19 new LRC bugs. We also discuss patching strategies of LRC bugs based on our study and bug-fixing experience.
Parity checking comprises a low-redundancy method for the design of reliable digital systems. While quite effective for detecting single-bit transmission or storage errors, parity encoding has not been widely used for...
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ISBN:
(纸本)0819445584
Parity checking comprises a low-redundancy method for the design of reliable digital systems. While quite effective for detecting single-bit transmission or storage errors, parity encoding has not been widely used for checking the correctness of arithmetic results because parity is not preserved during arithmetic operations and parity prediction requires fairly complex circuits in most cases. We propose a general strategy for designing parity-checked arithmetic circuits that takes advantage of redundant intermediate representations. Because redundancy is often used for high performance anyway, the incremental cost of our proposed method is quite small. Unlike conventional binary numbers, redundant representations can be encoded and manipulated in such a way that parity is preserved in each step. Additionally, lack of carry propagation ensures that the effect of a fault is localized rather than catastrophic. After establishing the framework for our parity-preserving transformations in computer arithmetic, we illustrate some applications of the proposed strategy to the design of parity-checked adder/subtractors, multipliers, and other arithmetic structures used in signal processing.
This study proposes an interconnected smart wearable device and enables the state of the machine to be quickly fed back to the operator. First, the internal parameters are obtained through the communication protocol p...
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ISBN:
(数字)9781665470506
ISBN:
(纸本)9781665470506
This study proposes an interconnected smart wearable device and enables the state of the machine to be quickly fed back to the operator. First, the internal parameters are obtained through the communication protocol provided by the CNC machine tool controller manufacturer. In addition, the interconnection function of the personal smart wearable device is set according to the work rights and responsibilities. Then, the error codes are defined according to the manual. The error code generated by the abnormality of the machine is sent to the Raspberry Pi through the industrial personal computer. The database records information about abnormal events, including machine numbers, timestamps, and error codes. However, each operator's smart wearable device will receive different messages. The experimental results show that the connection and information sharing between the machine and the smart wearable device is successful. The interconnection function and proxy mechanism can reduce the processing time of machine exceptions. In future research work, more complete experiments and analyses will be carried out, and more data will be used to highlight the value and contribution of the intelligent system.
Despite difficulties in general division, magnitude comparison, and sign detection, residue number system arithmetic has been used for many special-purpose systems in light of its parallelism and modularity for the mo...
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ISBN:
(纸本)0819445584
Despite difficulties in general division, magnitude comparison, and sign detection, residue number system arithmetic has been used for many special-purpose systems in light of its parallelism and modularity for the most common arithmetic operations of addition/subtraction and multiplication. Computation in RNS requires modular reduction, both for the initial conversion from binary to RNS and after each operation to bring the result back to within a valid residue range. Use of redundant residues simplifies this critical operation, leading to even faster arithmetic. One type of redundant mod-m residue, that keeps the representational redundancy to the minimum of 1 bit per residue, has the nearly symmetric range [-m, m) and allows two values for each pseudoresidue: (m) or (m) - m. We study the extent of simplification and speed-up in the modular reduction process afforded by such redundant residues and discuss its potential implications to the design of RNS arithmetic circuits. In particular, we show that besides cost and performance benefits, introduction of error checking and fault tolerance in arithmetic computations is facilitated when such redundant residues are used.
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