This paper presents an FPGA implementation for LDPC codes performance simulation. The goal is for fast evaluation of LDPC code to investigate the error floor. The hardware evaluation platform features by fast simulati...
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ISBN:
(纸本)9781424442461
This paper presents an FPGA implementation for LDPC codes performance simulation. The goal is for fast evaluation of LDPC code to investigate the error floor. The hardware evaluation platform features by fast simulation speed and high precision. The construction of the platform is described. The critical modules designed in the platform such as LDPC encoder, decoder, and AWGN noise generator are presented. As the result, a throughput of 120 Mbps is achieved and the BER curve can reach beyond 10(-11) within 10 hours.
We exploit the inherent information redundancy in the control path of Network-on-Chip (NoC) routers to manage transient errors, preventing packet loss and misrouting. Outputs of the routing arbitration units in NoC ro...
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We exploit the inherent information redundancy in the control path of Network-on-Chip (NoC) routers to manage transient errors, preventing packet loss and misrouting. Outputs of the routing arbitration units in NoC routers can be used to determine arbitration failures, because the valid arbitration outputs are a subset of all possible values. This feature is exploited to detect and correct logic and register errors in the router arbitration control path. The proposed method is complementary to other error management methods for NoC routers. An analytical reliability model of our method is provided, including parameters such as logic unit size, different error rates for logic gates and registers, and the location of faulty elements. Compared to triple-modular redundancy (TMR), the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total area and power by 43% and 64%, respectively. In the presented case studies, two traffic traces from the PARSEC benchmark suite are used to evaluate the average latency and energy consumption. Simulations performed on a 4 x 4 NoC show that our method reduces the average latency by up to 50% and reduces average energy by up to 70% compared to other methods.
error detection is a fundamental need in most computer networks and communication systems in order to combat the effect of noise. error detection techniques have also been incorporated with lossless data compression a...
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error detection is a fundamental need in most computer networks and communication systems in order to combat the effect of noise. error detection techniques have also been incorporated with lossless data compression algorithms for transmission across communication networks. In this paper, we propose to incorporate a novel error detection scheme into a Shannon optimal lossless data compression algorithm known as Generalized Luroth Series (GLS) coding. GLS-coding is a generalization of the popular Arithmetic coding which is an integral part of the JPEG2000 standard for still image compression. GLS-coding encodes the input message as a symbolic sequence on an appropriate 1D chaotic map Generalized Luroth Series (GLS) and the compressed file is obtained as the initial value by iterating backwards on the map. However, in the presence of noise, even small errors in the compressed file leads to catastrophic decodingerrors owing to sensitive dependence on initial values, the hallmark of deterministic chaos. In this paper, we first show that repetition codes, the oldest and the most basic error correction and detection codes in literature, actually lie on a Cantor set with a fractal dimension of 1/n, which is also the rate of the code. Inspired by this, we incorporate error detection capability to GLS-coding by ensuring that the compressed file (initial value on the chaotic map) lies on a Cantor set. Even a 1-bit error in the initial value will throw it outside the Cantor set, which can be detected while decoding. The rate of the code can be adjusted by the fractal dimension of the Cantor set, thereby controlling the error detection performance.
We present a powerful errorcontrol decoder which can be used in all kinds of digital versatile disk (DVD) systems. The decoder exploits the error information from the modulation decoder in order to increase the error...
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We present a powerful errorcontrol decoder which can be used in all kinds of digital versatile disk (DVD) systems. The decoder exploits the error information from the modulation decoder in order to increase the error correcting capability. We can identify that the modulation decoder in DVD system can detect errors more than 60% of total errors when burst errors are occurred. In results, for a decoded block, error correcting capability of the proposed scheme is improved up to 25% more than that of the original errorcontrol decoder. Also, a pipeline-balanced Reed-Solomon Product Code (RSPC) decoder with a low hardware complexity is designed to maximize the throughput. The maximum throughput of the RSPC decoder is 740 Mbps at 100 MHz and the number of gate counts is 20.3 K for RS(182, 172, 11) decoder and 30.7 K for RS(208, 192, 17) decoder, respectively.
Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements i...
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Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements in error control coding methods have seen a huge surge in using low-density parity-check (LDPC) code-based decoding algorithms to solve imperative issues related to reliable data transmission and reception. Till date, extensive research efforts have been consistently being made on LDPC codes which focus on algorithm-driven and hardware-realization-based approaches. The main intension of this research work is to provide an extensive systematic elucidation on the recent advancements in LDPC decoding algorithms. In addition, a thorough performance evaluation and analysis of several outstanding LDPC decoding techniques is presented. Finally, conclusions are drawn by summarizing the important research findings, interesting open problems, current challenges and broader perspectives for future directions of research.
We propose a system with image authentication and cross-recovery ability to protect a group of n given digital images. The system is a (r, n) threshold scheme (r is a prespecified threshold satisfying 2 <= r < n...
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We propose a system with image authentication and cross-recovery ability to protect a group of n given digital images. The system is a (r, n) threshold scheme (r is a prespecified threshold satisfying 2 <= r < n). Any r of these images can reconstruct the whole group of n images, but less than r images cannot. Therefore the system has cross-recovery ability because if some [up to (n-r)] images in the group are destroyed or lost in a distributed storage scheme or transmission mission, the destroyed or lost can be rebuilt vividly by the mutual support of r survived members. The design is composed of compression, a two-layer sharing, cryptographic hash function, and information hiding. (C) 2008 SPIE and IS&T.
This article proposes a rate-adaptive, two-tiered error-correction scheme (RATT-ECC) that provides strong reliability (1010x reduction in raw FIT rate) for an HBM-like 3D DRAM system. The tier-1 code is a strong symbo...
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This article proposes a rate-adaptive, two-tiered error-correction scheme (RATT-ECC) that provides strong reliability (1010x reduction in raw FIT rate) for an HBM-like 3D DRAM system. The tier-1 code is a strong symbol-based code that can correct errors due to small granularity faults and detect errors caused by large granularity faults;the tier-2 code is an XOR-based code that corrects errors detected by the tier-1 code. The rate-adaptive feature of RATT-ECC enables permanent bank failures to be handled through sparing. It can also be used to significantly reduce the refresh power consumption without decreasing reliability and timing performance.
Whilst the laboratory works at faculties providing education on the field of electronics and communication support the technical knowledge of students, they also develop their implementation abilities. The fact that t...
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Whilst the laboratory works at faculties providing education on the field of electronics and communication support the technical knowledge of students, they also develop their implementation abilities. The fact that there is less equipment requiring advanced technologies in laboratories, enforces the students to group works and thus limits working time and their contribution to the experiments. Contemporary computer technology provides the possibility for establishing alternative laboratories, environments in which the students can perform implementations without the restrictions of location and time. In this work, real time remote accessible experiment sets are prepared regarding coding techniques with errorcontrol. It is provided that the students can connect to the web based laboratory system via any computer on the LAN and make experiments. In this laboratory, the student will perform real time implementations without the restriction of location and time and strengthen their theoretical knowledge.
This paper proposes the novel joint coding suitable for dependable and secure systems. The proposed joint coding has three functions: data compression, public-key encryption and error control coding. This coding provi...
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This paper proposes the novel joint coding suitable for dependable and secure systems. The proposed joint coding has three functions: data compression, public-key encryption and error control coding. This coding provides very low encoding complexity due to realising only by simple matrix computation, which gives an efficient transmission of data in networks and a high speed execution in computers. In an encoding process, input data is firstly converted to a sparse sequence, which is then encoded using the encoding matrix generated by linear block codes and randomly constructed non-singular matrices. Decoding is performed based on error correction algorithm of the linear block codes. Evaluation shows that the encoder gate count of the proposed joint coding for still images is smaller than that of the conventional separate coding by 65.7%.
In this paper, a novel transmission scheme is developed to effectively combine parity bit selected spreading technique and MIMO-OFDM to obtain improved bit error rate performance in the presence of frequency selective...
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ISBN:
(纸本)9781457714146
In this paper, a novel transmission scheme is developed to effectively combine parity bit selected spreading technique and MIMO-OFDM to obtain improved bit error rate performance in the presence of frequency selective fading channels with low system complexity. Unlike conventional MIMO-OFDMA, where users are separated in different frequency bands (subchannels), and each user is coded separately using STBC or SFBC, the proposed new scheme enables multi access by joint code design across multiple antennas, subcarriers, and users. Such system will benefit from the combined space and frequency domain freedom as well as multiuser diversity. Hence, better spectrum efficiency is achieved while improving bit error rate performance with respect to signal-to-interference ratio.
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