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Performance analysis for coded CDMA systems

IEEE TRANSACTIONS ON INFORMATION THEORY 2003年第12期49卷 3282-3288页

作者： Zhang, JQ Univ New Hampshire Dept Elect & Comp Engn Durham NH 03824 USA

This correspondence analyzes the bit-error rate (BER) performance of coded synchronous code-division multiple-access (CDMA) systems assuming perfect channel state information (CSI) and optimal joint multiuser detection/decoding (OJMUDD). Our analysis is conducted in the same framework as that of uncoded systems. First, we derive the precise probability of an error event, then we provide an upper bound on the BER based on the sum of pairwise error probabilities, and, finally, we tighten the upper bound by considering decomposable error events. Many new concepts unique to coded systems are introduced. We propose to use quasi parity checks for identifying permissible error events, introduce the concept of compatible probability of error matrices, extend the list of conditions for identifying decomposable error events, and introduce the concept of conjugate sets to explore the symmetry among indecomposable error events. Simulation results are given along with theoretical predictions.

关键词： code-division multiple access (CDMA) error control coding joint multiuser detection and channel decoding multiuser detection performance analysis turbo decoding

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Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2016年第11期35卷 4060-4080页

作者： Sulek, Wojciech Silesian Tech Univ Akad 16 PL-44100 Gliwice Poland

Most of the recently proposed hardware realizations for non-binary low-density parity-check decoders are ASIC oriented as they employ multiplierless computation units. In this article, we present a different decoder design approach that is specifically intended for an FPGA implementation. We reformulate the mixed-domain FFT-BP decoding algorithm and develop a decoder architecture that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA, thus making use of all the types of FPGA resources. Then, the throughput limit achievable in a single FPGA by the proposed decoder is significantly increased. We also consider another important optimization of the decoder implementation, mainly an efficient realization of the permutation units and an approximated evaluation of the nonlinear functions of messages. Another motivation is to make the decoder easily scalable for FPGA devices of different sizes. To achieve this goal, the configurable semi-parallel decoder architecture is applied operating for the structured subclass of codes.

关键词： error control coding Low-density parity-check codes Non-binary codes LDPC decoding Decoder implementation

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Optimization of Unequal error Protection Rateless Codes for Multimedia Multicasting

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JOURNAL OF COMMUNICATIONS AND NETWORKS 2015年第3期17卷 221-230页

作者： Cao, Yu Blostein, Steven D. Chan, Wai-Yip Huawei Technol Canada Kanata ON K2K 3J1 Canada Queens Univ Dept Elect & Comp Engn Kingston ON K7L 3N6 Canada

Rateless codes have been shown to be able to provide greater flexibility and efficiency than fixed-rate codes for multicast applications. In the following, we optimize rateless codes for unequal error protection (UEP) for multimedia multicasting to a set of heterogeneous users. The proposed designs have the objectives of providing either guaranteed or best-effort quality of service (QoS). A randomly interleaved rateless encoder is proposed whereby users only need to decode symbols up to their own QoS level. The proposed coder is optimized based on measured transmission properties of standardized raptor codes over wireless channels. It is shown that a guaranteed QoS problem formulation can be transformed into a convex optimization problem, yielding a globally optimal solution. Numerical results demonstrate that the proposed optimized random interleaved UEP rateless coder's performance compares favorably with that of other recently proposed UEP rateless codes.

关键词： error control coding multimedia raptor codes unequal error protection video transmission

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Ambiguity resistant polynomial matrices

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LINEAR ALGEBRA AND ITS APPLICATIONS 1999年第1-3期286卷 19-35页

作者： Zhou, GC Xia, XG Univ Delaware Dept Elect & Comp Engn Newark DE 19716 USA

An N x K (N greater than or equal to K) ambiguity resistant (AR) matrix G(z) is an irreducible polynomial matrix of size N x K over a field F such that the equation EG(z) = G(z) V(z) with E an unknown constant matrix and V(z) an unknown polynomial matrix has only the trivial solution E = alpha I-N, V(z) = alpha I-K, where alpha is an element of F. AR matrices have been introduced and applied in modern digital communications as error control codes defined over the complex field. In this paper we systematically study AR matrices over an infinite field F. We discuss the classification of AR matrices, define their normal forms, find their simplest canonical forms, and characterize all (K + 1) x K AR matrices that are the most interesting matrices in the applications. (C) 1999 Elsevier Science Inc. All rights reserved.

关键词： irreducible matrix ambiguity resistant matrix polynomial matrix error control coding

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Performance analysis of ML-based feedback carrier phase synchronizers for coded signals

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2007年第3期55卷 1129-1136页

作者： Noels, Nele Steendam, Heidi Moeneclaey, Marc Univ Ghent Telecommun & Informat Proc Dept B-9000 Ghent Belgium

This paper considers carrier phase recovery in transmission systems with an iteratively decodable error-control code [turbo codes, low-density parity check (LDPC) codes], whose large coding gains enable reliable communication at very low signal-to-noise ratio (SNR). We compare three types of feedback phase synchronizers, which are all based upon the maximum-likelihood (ML) estimation principle: a data-aided (DA) synchronizer, a non-code-aided (NCA) synchronizer, and an iterative code-aided (CA) synchronizer. We introduce a blockwise forward-backward recursive phase estimator, and we show that the mean-square phase error (MSPE) of the NCA synchronizer equals that of the DA synchronizer when the carrier phase is constant and the loop filter gain is the same for both synchronizers. When the signal is affected by phase noise, the NCA synchronizer (as compared with the DA synchronizer) yields a larger MSPE due to phase fluctuations. We also show that, at the normal operating SNR of the considered code, the performance of the CA synchronizer is very close to that of a DA synchronizer that knows all transmitted symbols in advance.

关键词： carrier synchronization error control coding feedback phase estimation

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Low complexity bit-parallel systolic architecture for computing C+AB² over a class of GF(2^m)

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INTEGRATION-THE VLSI JOURNAL 2004年第3期37卷 167-176页

作者： Ting, YR Lu, EH Lee, JY Chang Gung Univ Dept Elect Engn Kweisan 333 Taoyuan Taiwan

This work presents a ringed bit-parallel systolic architecture for computing C + AB(2) over a class of GF(2(m)) based on the irreducible all one polynomial or the irreducible equally spaced polynomial of degree m, where A, B and C are elements in GF(2(m)). The ringed bit-parallel systolic multiplier over the class of GF(2) is free of global connections and requires fewer gates and input pins than the other relative multipliers proposed in Liu et al. (IEICE Trans. Fundam. E83-A (12) (2000) 2657) and Lee et al. (IEEE Trans. Circuits Syst. II 48(5) (2001) 519;15th IEEE Symposium on Computer Arithmetic (Arith-2001), Vail, CO, USA, June 2001, p. 51). Moreover, this ringed configuration can be easily implemented in VLSI systems by taking the advantage of three-dimensional routing. (C) 2004 Elsevier B.V. All rights reserved.

关键词： cryptography error control coding systolic multiplier finite field C + AB(2)

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Systolic and super-systolic multipliers for finite field GF(2^m) based on irreducible trinomials

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2008年第4期55卷 1031-1040页

作者： Meher, Pramod Kumar Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

Novel systolic and super-systolic architectures are presented for polynomial basis multiplication over GF(2(m)) based on irreducible trinomials. By suitable cut-set retiming, we have derived here an efficient bit-level-pipelined bit-parallel systolic design for binary field multiplication which requires fewer gates and registers and involves nearly half the time-complexity of the corresponding existing design. We have also suggested a digit-level-pipelined design, which involves lower latency, and fewer registers compared with the bit-level-pipelined structure. Moreover, we have proposed a super-systolic design consisting of a set of systolic arrays in a systolic-pipeline and a pipelined systolic-block design consisting of a pipelined blocks of concurrent systolic arrays. The super-systolic designs have the same average computation time and the same critical path as the proposed bit-level-pipelined design, but can be used to reduce the latency by a factor O(root m) at the cost of marginally higher number of XOR gates and bit-registers. The hardware complexities of proposed super-systolic designs are nearly three times that of the existing bit-parallel structures, but offer very high throughput compared with the others for large values of m. For the field orders m = 233 and m = 409, the proposed structures offer, respectively, ten and eleven times more throughput than the others.

关键词： elliptic curve cryptography (ECC) error control coding finite field finite-field multiplication Galois field irreducible trinomials systolic array very large-scale integration (VLSI)

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High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving

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IEICE TRANSACTIONS ON ELECTRONICS 2009年第6期E92C卷 867-874页

作者： Onizawa, Naoya Hanyu, Takahiro Gaudet, Vincent C. Tohoku Univ Elect Commun Res Inst Sendai Miyagi 9808577 Japan Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90 not CMOS technology, at a comparable BER.

关键词： error control coding LDPC codes sum-product algorithm asynchronous data transfer multiple-valued current-mode circuit

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Progressive image transmission with genetic algorithm-based optimization and multiple cyclic redundancy check structure

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JOURNAL OF ELECTRONIC IMAGING 2008年第2期17卷 023009-023009-9页

作者： Yao, Lei Cao, Lei Univ Mississippi Dept Elect Engn University MS 38677 USA

We consider the transmission of progressive image data over noisy channels when the coded packet size is fixed. The concatenated cyclic redundancy check (CRC) codes and rate-compatible punctured turbo codes are used for error control and detection. In such an application, the distortion-based optimal channel rate allocation for unequal error protection is complex. We first propose a suboptimal genetic algorithm-based method that not only largely reduces the optimization complexity but also obtains performance approaching to the results of a brute force search. In addition, because a large packet size is usually applied when turbo codes are used due to the fact that the coding gain is proportional to the packet size for a given code rate, a single remaining bit error after channel decoding may result in CRC failure and hence the discard of the entire packet Therefore, we further propose a multiple-CRC structure for certain data packets so that more correctly decoded data could be used in source decoding. The promising performance of the proposed scheme has been demonstrated through simulation. (C) 2008 SPIE and IS&T.

关键词： Distortion error control coding Genetic algorithms Image transmission Simulations

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EXIT Function Aided Design of Iteratively Decodable Codes for the Poisson PPM Channel

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IEEE TRANSACTIONS ON COMMUNICATIONS 2010年第12期58卷 3573-3582页

作者： Barsoum, Maged F. Moision, Bruce Fitz, Michael P. Divsalar, Dariush Hamkins, Jon CALTECH Jet Prop Lab Informat Proc Grp Pasadena CA USA Northrop Grumman Space Technol Redondo Beach CA 90278 USA Univ Calif Los Angeles Los Angeles CA 90095 USA

This paper presents and compares two iterative coded modulation techniques for deep-space optical communications using pulse-position modulation (PPM). The first code, denoted by SCPPM, consists of the serial concatenation of an outer convolutional code, an interleaver, a bit accumulator, and PPM. The second code, denoted by LDPC-PPM, consists of the serial concatenation of an LDPC code and PPM. We employ Extrinsic Information Transfer (EXIT) charts for their analysis and design. Under conditions typical of a communications link from Mars to Earth, SCPPM is 1 dB away from capacity, while LDPC-PPM is 1.4 dB away from capacity, at a Bit error Rate (BER) of approximately 10(-5). However, LDPC-PPM lends itself naturally to low latency parallel processing in contrast to SCPPM.

关键词： error control coding pulse position modulation optical modulation optical communication

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