This letter presents a hybrid error control and artifact detection (HECAD) mechanism which can be used to enhance the error resilient capabilities of the standard H.264/advanced video coding (AVC) codec. The proposed ...
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This letter presents a hybrid error control and artifact detection (HECAD) mechanism which can be used to enhance the error resilient capabilities of the standard H.264/advanced video coding (AVC) codec. The proposed solution first exploits the residual source redundancy to recover the most likelihood H.264/AVC bitstream. If error recovery is unsuccessful, the residual corrupted slices are then passed through a pixel-level artifact detection mechanism to detect the visually impaired macroblocks to be concealed. The proposed HECAD algorithm achieves overall peak signal-to-noise ratio gains between 0.4 dB and 4.5 dB relative to the standard with no additional bandwidth requirement. The cost of this solution translates in a marginal increase in the complexity of the decoder. In addition, this method can be applied in conjunction with other error resilient strategies and scales well with different encoding configurations.
The widely used code-excited linear prediction (CELP) paradigm relies on a strong interframe dependency which renders CELP-based codecs vulnerable to packet loss. The use of long-term prediction (LTP) or adaptive code...
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The widely used code-excited linear prediction (CELP) paradigm relies on a strong interframe dependency which renders CELP-based codecs vulnerable to packet loss. The use of long-term prediction (LTP) or adaptive codebooks (ACB) is the main source of interframe dependency in these codecs, since they employ the excitation from previous frames. After a frame erasure, previous excitation is unavailable and a desynchronization between the encoder and the decoder appears, causing an additional distortion which is propagated to the subsequent frames. In this paper, we propose a novel media-specific Forward errorcorrection (FEC) technique which retrieves LTP-resynchronization with no additional delay at the cost of a very small bit of overhead. In particular, the proposed FEC code contains a multipulse signal which replaces the excitation of the previous frame (i.e., ACB memory) when this has been lost. This multipulse description of the previous excitation is optimized to minimize the perceptual error between the synthesized speech signal and the original one. To this end, we develop a multipulse formulation which includes the additional CELP processing and, in addition, can cope with the presence of advanced LTP filters and the usual subframe segmentation applied in modern codecs. Finally, a quantization scheme is proposed to encode pulse parameters. Objective and subjective quality tests applied to our proposal show that the propagation error due to LTP filter can practically be removed with a very little bandwidth increase.
Efficient bit stream adaptation and resilience to packet losses are two critical requirements in scalable video coding for transmission over packet-lossy networks. Various scalable layers have highly distinct importan...
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Efficient bit stream adaptation and resilience to packet losses are two critical requirements in scalable video coding for transmission over packet-lossy networks. Various scalable layers have highly distinct importance, measured by their contribution to the overall video quality. This distinction is especially more significant in the scalable H.264/advanced video coding (AVC) video, due to the employed prediction hierarchy and the drift propagation when quality refinements are missing. Therefore, efficient bit stream adaptation and unequal protection of these layers are of special interest in the scalable H.264/AVC video. This paper proposes an algorithm to accurately estimate the overall distortion of decoder reconstructed frames due to enhancement layer truncation, drift/error propagation, and error concealment in the scalable H.264/AVC video. The method recursively computes the total decoder expected distortion at the picture-level for each layer in the prediction hierarchy. This ensures low computational cost since it bypasses highly complex pixel-level motion compensation operations. Simulation results show an accurate distortion estimation at various channel loss rates. The estimate is further integrated into a cross-layer optimization framework for optimized bit extraction and content-aware channel rate allocation. Experimental results demonstrate that precise distortion estimation enables our proposed transmission system to achieve a significantly higher average video peak signal-to-noise ratio compared to a conventional content independent system.
The decoding of a class of discrete cosine transform (DCT) and discrete sine transform (DST) codes that are maximum distance separable codes (MDS) is considered in this paper. These class of codes are considered for e...
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The decoding of a class of discrete cosine transform (DCT) and discrete sine transform (DST) codes that are maximum distance separable codes (MDS) is considered in this paper. These class of codes are considered for errorcorrection over real fields. All the existing algebraic decoding algorithms are capable of decoding only a subclass of these codes [which can be characterized into the Bose-Chaudhuri-Hocquenghem (BCH) form], and fails to decode the remaining even though they are MDS. In this paper, we propose a new generic algorithm along the lines of coding theoretic and subspace methods to decode the entire class of MDS DCT and DST codes. The proposed subspace approaches are similar to popular ESPRIT and MUSIC algorithms. The proposed algorithms also perform significantly better than the existing algorithms on the BCH-like subclass. A perturbation analysis is also presented to study the effect of various parameters on the error localization due to the quantization noise. Simulation results are presented to demonstrate the capability of proposed algorithms to decode the entire class and to perform significantly better on the BCH-like subclass than the existing algorithm under the influence of quantization noise.
Q-ary low-density parity-check (LDPC) codes, compared with binary ones, produce a better error performance but with a higher decoding complexity. Various solutions, such as speeding up single operations or reducing th...
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Q-ary low-density parity-check (LDPC) codes, compared with binary ones, produce a better error performance but with a higher decoding complexity. Various solutions, such as speeding up single operations or reducing the total number of operations, have been proposed for accelerating the decoding process. In this letter, we propose a modification to the extended min-sum (EMS) decoding algorithm. The aim is to improve the decoding speed without sacrificing any error performance over an additive white Gaussian noise (AWGN) channel environment.
We derive a simple formula to generate a wide-sense systematic generator matrix B for a Reed-Solomon code. Specifically, we generate the generator matrix B such that the columns with indices rho(1), rho(2), ..., rho(k...
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We derive a simple formula to generate a wide-sense systematic generator matrix B for a Reed-Solomon code. Specifically, we generate the generator matrix B such that the columns with indices rho(1), rho(2), ..., rho(k) are the columns of the identity matrix I-k. One possible application of these wide-sense matrices is erasures-only decoding.
A novel design approach is proposed for low-density parity-check convolutional codes (LDPC-CCs), that jointly optimizes the code, encoder and decoder to achieve high-throughput parallel encoding and decoding. A series...
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A novel design approach is proposed for low-density parity-check convolutional codes (LDPC-CCs), that jointly optimizes the code, encoder and decoder to achieve high-throughput parallel encoding and decoding. A series of implementation-oriented constraints are applied to construct architecture-aware (AA) codes by introducing algebraic structures into the parity-check matrix. The resulting AA codes have bit error rate performance comparable to other published LDPC-CCs. Given these AA LDPC-CCs, new architectures are proposed for a parallel LDPC-CC encoder with built-in termination and an LDPC-CC decoder that is parallel in the node dimension as well as pipelined in the iteration dimension. ASIC synthesis results for a 90-nm CMOS process show that the proposed encoder and the decoding processor achieve 2.0-Gbps throughputs at 250-MHz clock frequencies within silicon areas of 0.1 mm(2) and 1 mm(2) respectively.
Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation. errorcorrection algorithms are often implemented in hardware for ...
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Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation. errorcorrection algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However hardware implementation of LDPC decoders using traditional hardware description language (HDL) based approach is a complex and time consuming task. This paper presents an efficient high level approach to designing LDPC decoders using a collection of high level modelling tools. The proposed new methodology supports programmable logic design starting from high level modelling all the way up to FPGA implementation. The methodology has been used to design and implement representative LDPC decoders. A comprehensive testing strategy has been developed to test the designed decoders at various levels. The simulation and implementation results presented in this paper prove the validity and productivity of the new high level design approach.
An implementation of the turbo coding technique for data error detection and correction in data transmission is presented. The turbo coding technique is known to be efficient in data transmission adding redundant pari...
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ISBN:
(纸本)9783642167607
An implementation of the turbo coding technique for data error detection and correction in data transmission is presented. The turbo coding technique is known to be efficient in data transmission adding redundant parity that provides a high errorcorrection capacity decreasing the number of erroneous bits for low signal to noise ratios increasing the number of iterations. The turbo encoder and turbo decoder were implemented in a FPGA development system. The design is oriented to reach a transmission speed near to the theoretical Shannon's capacity of the communication channel and minimum possible energy consumption using only the FPGA resources without external memories.
This paper considers the joint source channel coding using a new class of DFT codes which we refer to as Hermitian symmetric DFT (HSDFT) codes. A new decoding algorithm for decoding of HSDFT codes is presented. With t...
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ISBN:
(纸本)9781424453092
This paper considers the joint source channel coding using a new class of DFT codes which we refer to as Hermitian symmetric DFT (HSDFT) codes. A new decoding algorithm for decoding of HSDFT codes is presented. With this new decoding algorithm and an appropriate transmission scheme, HSDFT codes are capable of correcting more burst errors than the capacity of any maximum distance separable (MDS) code. Experimental results obtained by transmission of image over binary symmetric channel and Gilbert-Elliot channel are also presented, which show that HSDFT codes perform similar to the existing DFT class of codes on a binary symmetric channel while it performs consistently better (by around 2dB) on a Gilbert-Elliot like channel.
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