Radiation-induced soft error rate (SER) degrades the reliability of static random access memory (SRAM)-based field programmable gate arrays (FPGAs). This paper presents a new built-in 2-D Hamming product code (2 D HPC...
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Radiation-induced soft error rate (SER) degrades the reliability of static random access memory (SRAM)-based field programmable gate arrays (FPGAs). This paper presents a new built-in 2-D Hamming product code (2 D HPC) scheme to provide reliable operation of SRAM-based FPGAs in hostile operating environments such as space. Multibit errorcorrection capability of our built-in 2-D HPC can improve the reliability, and hence, system availability, by orders of magnitude. Simulation results show that the large number of errorcorrection capability of 2-D HPC can recover configuration bits without depending on an external memory preserving a golden copy of the configuration bits. To provide efficient 2-D HPC in a built-in logic, we also propose a new 2-D SRAM buffer. Using the proposed multibit errorcorrection scheme, system availability of an SRAM-based FPGA can be more than 99.9999999% with SRAM cell failures in 1 billion h of operation of 7.
We present a throughput analysis for the memory automatic repeat request (ARQ) schemes with self-decodable frame retransmissions, taking into account frame header and frame acknowledgment failure probability. A lower ...
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We present a throughput analysis for the memory automatic repeat request (ARQ) schemes with self-decodable frame retransmissions, taking into account frame header and frame acknowledgment failure probability. A lower bound on the throughput is obtained for a very general class of schemes which encompasses many of those proposed in the literature. Numerical results are given for several example systems, and suitable header and acknowledgment forward errorcorrection (FEC) encodings are determined.
In this paper, we consider the general design criteria, properties and explicit code design procedures for cooperative multiple trellis coded modulation (CMTCM) schemes over Rayleigh fading channels. The cooperative s...
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In this paper, we consider the general design criteria, properties and explicit code design procedures for cooperative multiple trellis coded modulation (CMTCM) schemes over Rayleigh fading channels. The cooperative system of interest utilizes the decode and forward protocol based on orthogonal transmissions from the cooperating terminals to the destination. We design full diversity cooperative multiple trellis codes using asymmetric constellations that at a frame error probability of 10(-3) provide around 10-12 dB gains over non-cooperative coded modulation without sacrificing the data rate and/or bandwidth efficiency. This is achieved by expanding the baseline constellation used in the non-cooperative transmission, designing the signal constellation to be asymmetric, and adopting multiple mappings among users. The consistent performance gains due to coding, asymmetry, and mappings of symbols onto the constellation are evaluated in terms of the frame error probability. We present simulation results that support the theoretical designs and illustrate the viability of the proposed cooperative MTCM technique.
There has been a rejuvenated interest in the use of non-equally spaced (irregular) constellations after promising performance results were demonstrated compared with the conventional lattice constellations. This paper...
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There has been a rejuvenated interest in the use of non-equally spaced (irregular) constellations after promising performance results were demonstrated compared with the conventional lattice constellations. This paper investigates the use of the irregular constellations in convolutionally coded systems. To enable the use of such irregular constellations in the presence of convolutional encoders, we derive a bit-error-rate (BER) upper bound expression for the downlink of the coded transmit maximum ratio combining systems operating in Nakagami-m fading environments. In addition, the analysis is extended to turbo trellis-coded modulation scenarios in which the convolutional encoders are used as the constituent codes. We demonstrate, via simulation, that commonly used performance analysis techniques in the literature fail to provide a valid BER bound in coded cases where quasi-regularity is not satisfied. In contrast, the technique proposed herein does not require the chosen pair of constellation and encoder to be quasi-regular. Furthermore, the system model includes a provision for multiple orthogonal transmission stages with different numbers of transmit antennas. Antenna correlation as well as distributed transmission is also supported by the model. Simulation results demonstrate the accuracy of the derived analytical results for a wide range of system scenarios.
In joint source-channel arithmetic coding (JSCAC) schemes, additional redundancy may be introduced into an arithmetic source code in order to be more robust against transmission errors. The purpose of this work is to ...
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In joint source-channel arithmetic coding (JSCAC) schemes, additional redundancy may be introduced into an arithmetic source code in order to be more robust against transmission errors. The purpose of this work is to provide analytical tools to predict and evaluate the effectiveness of that redundancy. Integer binary Arithmetic coding (AC) is modeled by a reduced-state automaton in order to obtain a bit-clock trellis describing the encoding process. Considering AC as a trellis code, distance spectra are then derived. In particular, an algorithm to compute the free distance of an arithmetic code is proposed. The obtained code properties allow to compute upper bounds on both bit error and symbol error probabilities and thus to provide an objective criterion to analyze the behavior of JSCAC schemes when used on noisy channels. This criterion is then exploited to design efficient error-correcting arithmetic codes. Simulation results highlight the validity of the theoretical error bounds and show that for equivalent rate and complexity, a simple optimization yields JSCACs that outperform classical tandem schemes at low to medium SNR.
Displayed gray level of a plasma display panel (PDP)is often different from the intended target gray level due to the variation of the line load (the number of on-cells on a scan line). The conventional gray level gen...
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Displayed gray level of a plasma display panel (PDP)is often different from the intended target gray level due to the variation of the line load (the number of on-cells on a scan line). The conventional gray level generation algorithm does not take this difference into consideration and may deteriorate the displayed image quality. In this paper, luminance ratio variations that depend on the line load are formulated as the third-order regression equations for red, green and blue colors, respectively. Based on these equations, this paper proposes a new gray-level generation algorithm to reduce gray-level errors caused by the variation of the line load. The proposed algorithm performs the conventional algorithm three times with new weight vectors (i.e., the expected gray levels of subfields) adjusted based on the-detected error of the previous run of the conventional algorithm. Simulations and experiments with a 50-in PDP show significant error reductions, including a 75.6% improvement of the mean absolute error evaluated with nine video sequences.
An interleaving technique is proposed that is memory, delay, and packet efficient for demand assignment multiple-access, packet-switched transmission with frequency-hopped survivably interleaved signals over jammed or...
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An interleaving technique is proposed that is memory, delay, and packet efficient for demand assignment multiple-access, packet-switched transmission with frequency-hopped survivably interleaved signals over jammed or scintillated radio channels. This hybrid interleaving scheme concatenates the convolutional interleaver and the block interleaver.
Current wireless systems offer various use-cases where conventional channel capacity focused performance criteria might not apply. Following the similar perspective, convolutional encoding can find more room due to it...
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Current wireless systems offer various use-cases where conventional channel capacity focused performance criteria might not apply. Following the similar perspective, convolutional encoding can find more room due to its low complexity and low decoding delay. Besides, it has been also shown that error performance of a convolutional encoder can be improved further by using adaptive irregular constellations. A new performance measure, data-oriented approach, was recently proposed for the transmission of small data packets, i.e. mission-critical IoT applications, over fading channels. In this letter, delay performance gain resulting from convolution coding optimized irregular constellations is investigated. Then, we derive a new performance criterion based on delay and finite block length constraints. Based on this criterion, we design irregular constellations together with convolutional coding for short packet transmission.
In this paper we propose a new method for designing the spreading permutations based on space time block code matrices for MIMO-CDMA systems. The new designs improve the bit error rate (BER) compared to MIMO-CDMA syst...
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In this paper we propose a new method for designing the spreading permutations based on space time block code matrices for MIMO-CDMA systems. The new designs improve the bit error rate (BER) compared to MIMO-CDMA systems that use spreading permutations based on T-designs. This BER improvement comes without any increase in system complexity..
Soft-decision forward errorcorrection (SD-FEC) and its practical implementation for 100 Gb/s digital coherent systems are discussed. In applying SD-FEC to a digital coherent transponder, the configuration of the fram...
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Soft-decision forward errorcorrection (SD-FEC) and its practical implementation for 100 Gb/s digital coherent systems are discussed. In applying SD-FEC to a digital coherent transponder, the configuration of the frame structure of the FEC becomes a key issue. We present a triple-concatenated FEC, with a pair of concatenated hard-decision FEC (HD-FEC) further concatenated with an SD-based low-density parity-check (LDPC) code for 20.5% redundancy. In order to evaluate error correcting performance of SD-based LDPC code. We implement the entire 100 Gb/s throughput of LDPC code on field programmable gate arrays (FPGAs) based hardware emulator. The proposed triple-concatenated FEC can achieve a Q-limit of 6.4 dB and a net coding gain (NCG) of 10.8 dB at a post-FEC bit error ratio (BER) of 10 (15) is expected. In addition, we raise an important question for the definition of NCG in digital coherent systems with and without differential quadrature phase-shift keying (QPSK) coding, which is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms. (C) 2011 Elsevier Inc. All rights reserved.
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