This letter presents a novel variable-rate error control design algorithm matched to full-search vector quantizers (VQ's) for robust transmission. In the algorithm, different locations of binary strings obtained f...
详细信息
This letter presents a novel variable-rate error control design algorithm matched to full-search vector quantizers (VQ's) for robust transmission. In the algorithm, different locations of binary strings obtained from VQ encoders are protected by channel codes with different protection levels. The degree of protection at each location is determined by a genetic programming technique minimizing the end-to-end average distortion of transmission systems. The technique outperforms the equal error protection method. Moreover, as compared with full search algorithm for optimal unequal error protection, our technique attains comparable performance with significantly lower computational complexities.
Soft-decision forward errorcorrection (SD-FEC) and its practical implementation for 100 Gb/s digital coherent systems are discussed. In applying SD-FEC to a digital coherent transponder, the configuration of the fram...
详细信息
Soft-decision forward errorcorrection (SD-FEC) and its practical implementation for 100 Gb/s digital coherent systems are discussed. In applying SD-FEC to a digital coherent transponder, the configuration of the frame structure of the FEC becomes a key issue. We present a triple-concatenated FEC, with a pair of concatenated hard-decision FEC (HD-FEC) further concatenated with an SD-based low-density parity-check (LDPC) code for 20.5% redundancy. In order to evaluate error correcting performance of SD-based LDPC code. We implement the entire 100 Gb/s throughput of LDPC code on field programmable gate arrays (FPGAs) based hardware emulator. The proposed triple-concatenated FEC can achieve a Q-limit of 6.4 dB and a net coding gain (NCG) of 10.8 dB at a post-FEC bit error ratio (BER) of 10 (15) is expected. In addition, we raise an important question for the definition of NCG in digital coherent systems with and without differential quadrature phase-shift keying (QPSK) coding, which is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms. (C) 2011 Elsevier Inc. All rights reserved.
Recently, there has been intensive focus on turbo product codes (TPCs) which have low decoding complexity and achieve near-optimum performances at low signal-to-noise ratios. Different than the original TPC decoder, w...
详细信息
Recently, there has been intensive focus on turbo product codes (TPCs) which have low decoding complexity and achieve near-optimum performances at low signal-to-noise ratios. Different than the original TPC decoder, which performs row and column decoding in a serial fashion, we propose a parallel decoder structure. Simulation results show that with this approach, decoding latency of TPCs can be halved while maintaining virtually the same performance level.
Reed-Solomon (RS) error-correcting (EC) codes are often proposed for communication systems requiring burst and/or erasure correction capabilities. In most cases, the modulation symbol size is fixed a priori, Therefore...
详细信息
Reed-Solomon (RS) error-correcting (EC) codes are often proposed for communication systems requiring burst and/or erasure correction capabilities. In most cases, the modulation symbol size is fixed a priori, Therefore, the effective application of RS coding implies proper matching of the code symbol size with the modulation symbol size, Previous results have assumed that the RS codeword symbol size is an integer multiple of the modulation symbol size or have been based on simple approximations, In this paper, the exact symbol error probability with K-bit M-ary modulation symbols and q-bit RS codeword symbols is presented.
A class of concatenated block codes, called generalized error-locating (GEL) codes, is proposed for errorcorrection in digital magnetic storage systems. GEL codes are suited for high code rate applications with low-c...
详细信息
A class of concatenated block codes, called generalized error-locating (GEL) codes, is proposed for errorcorrection in digital magnetic storage systems. GEL codes are suited for high code rate applications with low-complexity (hard input) decoding algorithms. They offer high flexibility and can be adjusted to a variety of different situations. In this paper, we use as an example a (precoded) PR4 channel and consider GEL codes with BCH and Reed-Solomon component codes. Simulation results give bit error rates with and without constrained codes.
The sector failure rate (SFR) is extremely small at normal operating conditions of hard disk drives. In practice, it cannot be obtained by counting as that would require prohibitively large simulation times. Therefore...
详细信息
The sector failure rate (SFR) is extremely small at normal operating conditions of hard disk drives. In practice, it cannot be obtained by counting as that would require prohibitively large simulation times. Therefore, appropriate statistical models characterizing the distribution of error symbols are used in order to estimate the SFR. In this paper, we look at the underlying philosophy of existing estimation methods and classify them into macroscopic and microscopic types. We observe that the microscopic approach is well suited for certain iterative channels.
This letter presents a hybrid error control and artifact detection (HECAD) mechanism which can be used to enhance the error resilient capabilities of the standard H.264/advanced video coding (AVC) codec. The proposed ...
详细信息
This letter presents a hybrid error control and artifact detection (HECAD) mechanism which can be used to enhance the error resilient capabilities of the standard H.264/advanced video coding (AVC) codec. The proposed solution first exploits the residual source redundancy to recover the most likelihood H.264/AVC bitstream. If error recovery is unsuccessful, the residual corrupted slices are then passed through a pixel-level artifact detection mechanism to detect the visually impaired macroblocks to be concealed. The proposed HECAD algorithm achieves overall peak signal-to-noise ratio gains between 0.4 dB and 4.5 dB relative to the standard with no additional bandwidth requirement. The cost of this solution translates in a marginal increase in the complexity of the decoder. In addition, this method can be applied in conjunction with other error resilient strategies and scales well with different encoding configurations.
We propose a Viterbi-type decoder for tailbiting trellis codes that works by traversing the tailbiting circle somewhat more than once. The traversal is the least possible for any bounded distance Viterbi decoder. Proc...
详细信息
We propose a Viterbi-type decoder for tailbiting trellis codes that works by traversing the tailbiting circle somewhat more than once. The traversal is the least possible for any bounded distance Viterbi decoder. Procedures are given that compute this minimum. Unlike previous decoders of the type, the new scheme does not suffer limit cycles or from pseudocodewords. The bit-error rate is compared to that of Bahl-Cocke-Jelinek-Raviv and maximum-likelihood decoding.
In this paper, a packaged integrated coherent receiver and optical front-end for soft decision based on 25 Gbaud/s quadrature phase-shift keying (QPSK) is investigated for on-chip applications. The front-end consists ...
详细信息
In this paper, a packaged integrated coherent receiver and optical front-end for soft decision based on 25 Gbaud/s quadrature phase-shift keying (QPSK) is investigated for on-chip applications. The front-end consists of a 90 degrees hybrid, balanced photodetectors, and unbalanced couplers monolithically integrated in a CMOS compatible silicon-on-insulator technology. The silicon photonic device is packaged onto a ceramic substrate with RF and dc connectors. The proposed front-end is an example of integration of system on chip. The integrated solution is able to provide 6.2 dB performance improvements over uncoded system without errorcorrection. The front-end outperforms optical system with hard-decision forward errorcorrection by 2.2 dB at the BER of 10(-7).
This paper considers the detection of coded phase-shift keying signals subjected to additive white Gaussian noise and oscillator phase noise. We propose a detector that partitions the received frame into smaller block...
详细信息
This paper considers the detection of coded phase-shift keying signals subjected to additive white Gaussian noise and oscillator phase noise. We propose a detector that partitions the received frame into smaller blocks and models the unknown phasor variations over each block as a truncated discrete cosine transform (DCT) expansion. Detection and decoding are iteratively performed between a soft-input soft-output (SISO) demodulator, a SISO demapper, and a SISO decoder based on the sum-product algorithm and the factor graph framework, whereas the expectation-maximization algorithm is used in the demodulator for the DCT coefficients estimation. The resulting demodulator is shown to have an excellent performance/complexity tradeoff and to be well-suited for parallel processing on multiple cores.
暂无评论