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Reduced complexity hard- and soft-input BCH decoding with applications in concatenated codes

IET CIRCUITS DEVICES & SYSTEMS 2021年第3期15卷 284-296页

作者： Freudenberger, Juergen Bailon, Daniel Nicolas Safieh, Malek Univ Appl Sci Inst Syst Dynam ISD HTWG Konstanz Constance Germany

error correction coding for optical communication and storage requires high rate codes that enable high data throughput and low residual errors. Recently, different concatenated coding schemes were proposed that are based on binary BCH codes with low error correcting capabilities. In this work, low-complexity hard- and soft-input decoding methods for such codes are investigated. We propose three concepts to reduce the complexity of the decoder. For the algebraic decoding we demonstrate that Peterson's algorithm can be more efficient than the Berlekamp-Massey algorithm for single, double, and triple error correcting BCH codes. We propose an inversion-less version of Peterson's algorithm and a corresponding decoding architecture. Furthermore, we propose a decoding approach that combines algebraic hard-input decoding with soft-input bit-flipping decoding. An acceptance criterion is utilised to determine the reliability of the estimated codewords. For many received codewords the stopping criterion indicates that the hard-decoding result is sufficiently reliable, and the costly soft-input decoding can be omitted. To reduce the memory size for the soft-values, we propose a bit-flipping decoder that stores only the positions and soft values of a small number of code symbols. This method significantly reduces the memory requirements and has little adverse effect on the decoding performance.

关键词： decoding approach Berlekamp-Massey algorithm error correction coding triple error correcting BCH codes soft-input BCH decoding optical communication low error correcting capabilities double error correcting BCH codes error correction BCH codes decoding concatenated coding schemes soft-values bit-flipping decoder binary codes Peterson's algorithm high data throughput low-complexity hard-input decoding methods error correction codes single error correcting BCH codes low residual errors concatenated codes soft values reduced complexity hard-input BCH decoding soft-input bit-flipping decoding low-complexity soft-input decoding methods code symbols algebraic hard-input decoding high rate codes binary BCH codes decoding architecture decoding performance soft-input decoding parity check codes algebraic decoding

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Effect of conductance variability on resistor-logic demultiplexers for nanoelectronics

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2006年第5期5卷 446-454页

作者： Kuekes, Philip J. Robinett, Warren Williams, R. Stanley Hewlett Packard Labs Palo Alto CA 94304 USA

On a mixed-scale nanoelectronic crossbar, in which nanowires cross CMOS-scale wires at right angles, a demultiplexer circuit may be laid out using configurable resistors at the cross-point junctions. This circuit can function as an interface between conventional CMOS microelectronic circuitry and the smaller nanocircuitry by allowing a few CMOS address lines to control a much larger number of nanowires. The voltage margin properties of these resistor-demultiplexers can be improved by basing them on error-correcting codes. In any real fabrication process, the conductances of the resistors in the demultiplexer circuit will be distributed over a range of values. Using simulation, we investigate how variability in the conductances affects the voltages on the output lines of the demultiplexer, and the related voltage margin of the overall circuit. The simulation results provide a simple quantitative relationship revealing that the voltage variability is smaller than the component variability.

关键词： demultiplexing error correction coding nanotechnology resistive circuits voltage dividers

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Improved coding-Theoretic and Subspace-Based Decoding Algorithms for a Wider Class of DCT and DST Codes

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2010年第2期58卷 695-708页

作者： Kumar, A. Anil Makur, Anamitra Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore

The decoding of a class of discrete cosine transform (DCT) and discrete sine transform (DST) codes that are maximum distance separable codes (MDS) is considered in this paper. These class of codes are considered for error correction over real fields. All the existing algebraic decoding algorithms are capable of decoding only a subclass of these codes [which can be characterized into the Bose-Chaudhuri-Hocquenghem (BCH) form], and fails to decode the remaining even though they are MDS. In this paper, we propose a new generic algorithm along the lines of coding theoretic and subspace methods to decode the entire class of MDS DCT and DST codes. The proposed subspace approaches are similar to popular ESPRIT and MUSIC algorithms. The proposed algorithms also perform significantly better than the existing algorithms on the BCH-like subclass. A perturbation analysis is also presented to study the effect of various parameters on the error localization due to the quantization noise. Simulation results are presented to demonstrate the capability of proposed algorithms to decode the entire class and to perform significantly better on the BCH-like subclass than the existing algorithm under the influence of quantization noise.

关键词： Channel coding discrete cosine transform (DCT) codes error correction coding joint source-channel coding subspace algorithms

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Packet access using DS-CDMA with frequency-domain equalization

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 2006年第1期24卷 161-170页

作者： Garg, D Adachi, F Tohoku Univ Dept Elect & Commun Engn Sendai Miyagi 980 Japan Tohoku Univ Dept Elect & Commun Engn Sendai Miyagi 9808579 Japan

The next-generation mobile communications system is anticipated to support very high-speed data rates exceeding several tens megabits per second. In this paper, we consider high-speed downlink packet access for direct-sequence code-division multiple access (DS-CDMA) as in third-generation wideband code-division multiple-access systems. Adaptive modulation and coding (AMC), multicode operation and hybrid automatic repeat request (HARQ) will be the enabling technologies. With such high-speed data transmissions, however, multicode operation severely suffers from the loss of orthogonality among the spreading codes since the wireless channel becomes severely frequency-selective. In this paper, we apply frequency-domain equalization (FDE) based on minimum mean-square error (MMSE) criterion instead of conventional rake combining for receiving the packet. A new MMSE-FDE weight is derived for packet combining. The throughput in a frequency-selective Rayleigh-fading channel is evaluated by computer simulation for Chase combining and incremental redundancy (IR) packet combining. It is shown that the use of MMSE-FDE for the reception of multicode DS-CDMA packet gives an improved throughput irrespective of the channel's frequency-selectivity.

关键词： adaptive modulation coding (AMC) automatic repeat request direct-sequence code-division multiple access (DS-CDMA) equalizers error correction coding hybrid automatic repeat request (HARQ) high-speed downlink packet access (HSDPA) minimum mean-square error frequency-domain equalization (MMSE-FDE) mobile communication multicode

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Dynamic Write-Voltage Design and Read-Voltage Optimization for MLC NAND Flash Memory

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China Communications 2024年第12期21卷 297-308页

作者： Cai Runbin Fang Yi Shi Zhifang Dai Lin Han Guojun School of Information Engineering Guangdong University of TechnologyGuangdong 510006China

To mitigate the impact of noise and inter-ference on multi-level-cell(MLC)flash memory with the use of low-density parity-check(LDPC)codes,we propose a dynamic write-voltage design scheme con-sidering the asymmetric property of raw bit error rate(RBER),which can obtain the optimal write voltage by minimizing a cost *** order to further improve the decoding performance of flash memory,we put forward a low-complexity entropy-based read-voltage optimization scheme,which derives the read voltages by searching for the optimal entropy value via a log-likelihood ratio(LLR)-aware cost *** results demonstrate the superiority of our proposed dynamic write-voltage design scheme and read-voltage optimization scheme with respect to the existing counterparts.

关键词： error correction coding multi-level-cell(MLC) NAND flash memory read voltage write voltage

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Multidimensional Modulation and coding in Optical Transport

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2017年第4期35卷 876-884页

作者： Karlsson, Magnus Agrell, Erik Chalmers Univ Technol Dept Microtechnol & Nanosci Photon Lab SE-41296 Gothenburg Sweden Chalmers Univ Technol Dept Signals & Syst SE-41296 Gothenburg Sweden

This paper reviews the performance of optimized modulation formats in two, four, and eight dimensions. We present performance (lower bounds) for higher dimensions by exploiting known performance of binary block codes. Ultimately, the achievable information rates of given modulation formats and receiver types are limited by the mutual information and generalized mutual information. We exemplify how these metrics can be used for system performance as well as to quantify the performance differences between four types of systems, using hard or soft decision on bits or symbols.

关键词： Coded modulation error correction coding fiber optic communications modulation

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Message length adaptive LDPC codes

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DIGITAL SIGNAL PROCESSING 2012年第6期22卷 1107-1112页

作者： Tiwari, Honey Durga Cho, Yong Beom Konkuk Univ Dept Elect Engn Seoul 143701 South Korea

LDPC codes achieve better performance and lower decoding complexity than turbo codes, with a major drawback of high encoding complexity. The encoder generator matrix is derived from the inverse of portion of parity check matrix. If the message length is changed, the structure of parity check matrix is modified and hence, the generator matrix must be re-computed. This increases the encoding complexity as the computation of matrix inverse is time and resource consuming operation. In this paper, we consider the encoding problem for LDPC codes as the complexity of encoding is essentially quadratic wills respect to the block length. Using an efficient encoding method proposed by Richardson and Urbanke, we propose a systematic procedure to construct parity check matrix and generator matrix such that with change in message length, the re-computation for constructing generator matrix is avoided. The presented design uses fixed sub-matrices to construct a semi-random parity check matrix. The resultant design will reduce the pre-computation time of converting parity check matrix to generator matrix. The reported encoder reduces encoding time without the loss of coding gain and Bit error Rate (BER) performance. (C) 2012 Elsevier Inc. All rights reserved.

关键词： error correction coding Low-density parity check codes Permutation matrix

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Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2008年第11期55卷 3628-3640页

作者： Chen, Zhengang Brandon, Tyler L. Bates, Stephen Elliott, Duncan G. Cockburn, Bruce F. Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

Low-density parity-check convolutional codes (LDPC-CCs) have demonstrated comparable error-correcting performance to LDPC block codes (LDPC-BCs). However, the LDPC-CC encoder requires termination when applied to finite-length data frames to ensure that the trailing information bits are fully protected. In this paper, the LDPC-CC encoder design is investigated, and a novel termination scheme is proposed. Starting from any encoder state, the proposed scheme is capable of generating a termination sequence in hardware without padding, thus minimizing the rate loss due to termination. A high-speed architecture for LDPC-CC encoders with built-in termination is proposed. Synthesis results for LDPC-CCs of code memory size up to 512 demonstrate maximum encoding throughputs of around 1 Gb/s for a 90-nm CMOS technology. The implementation cost for such encoders is shown to be reasonably low for average-sized LDPC-CCs.

关键词： Application-specific integrated circuits (ASICs) convolutional codes error correction coding high-speed integrated circuits low-density parity-check (LDPC) codes trellis termination

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An adaptive hybrid ARQ scheme

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WIRELESS PERSONAL COMMUNICATIONS 2000年第3期12卷 297-311页

作者： Kallel, S Bakhtiyari, S Link, R Univ British Columbia Dept Elect & Comp Engn Vancouver BC V6T 1Z4 Canada

A hybrid ARQ in which the transmitter adaptively selects an FEC code according to the channel condition is presented and analyzed. The code is selected according to the past transmissions and acknowledgements by an algorithm which is a generalization of that in [1]. The throughput is obtained as a function of the frame error rate for a general system employing the adaptive hybrid ARQ with acknowledgements that arrive instantly on an error-free return channel. The throughput is obtained as a function of the signal-to-noise ratio for an example quad rate system employing convolutional codes with non-coherent frequency shift keying over the uncorrelated Rayleigh fading channel. This allows the best choice for the parameters of the algorithm to be made. In the case that the channel bit errors are independent, the generalization offers performance improvement of less than 10% over that in [1]. But when the channel errors are bursty, as in the case of Rayleigh fading with finite bit interleaving, the generalization offers throughput improvement as high as 24%. We go on to consider incorporating code combining with the adaptive scheme to form an adaptive memory hybrid ARQ. Simulation of a system using complementary punctured convolutional codes with 4 code rates shows that 2-level code combining can extend the adaptive scheme's useful throughput into the low SNR region by approximately 4 dB.

关键词： ARQ Hybrid ARQ Adaptive ARQ adaptive error control Memory ARQ error correction coding throughput code combining

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Hybrid Optical/RF Channels: Characterization and Performance Study using Low Density Parity Check Codes

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IEEE TRANSACTIONS ON COMMUNICATIONS 2009年第11期57卷 3288-3297页

作者： Tapse, Hrishikesh Borah, Deva K. New Mexico State Univ Klipsch Sch Elect & Comp Engn Las Cruces NM 88003 USA

A hybrid channel, consisting of a free space optical (FSO) link and a parallel radio frequency (RF) link, is considered. The FSO link carries most of the transmitted data while leaving only a small fraction of the data to be carried by the RF link. It is first shown that the capacity of the proposed hybrid structure is much higher than the capacity of a single FSO link. Next the performance of the hybrid channel is studied using a low density parity check code. A density evolution strategy for the hybrid channel is derived and a Gaussian approximation technique is presented. Using these techniques, the conditions for the convergence of the message passing algorithm in terms of minimum data carrying rate through the RF link are derived. Finally, numerical results showing the benefits of the hybrid channel under various channel conditions are presented.

关键词： error correction coding optical communications on-off keying message passing phase shift keying

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