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The sextuply shortened binary Golay code is optimal

DESIGNS codeS AND CRYPTOGRAPHY 2019年第2-3期87卷 341-347页

作者： Ostergard, Patric R. J. Aalto Univ Sch Elect Engn Dept Commun & Networking POB 15400 Aalto 00076 Finland

The maximum size of unrestricted binary three-error-correcting codes has been known up to the length of the binary Golay code, with two exceptions. Specifically, denoting the maximum size of an unrestricted binary code of length n and minimum distance d by A(n,d), it has been known that 64A(18,8)68 and 128A(19,8)131. In the current computer-aided study, it is shown that A(18,8)=64 and A(19,8)=128, so an optimal code is obtained even after shortening the extended binary Golay code six times.

关键词： Classification Clique Double counting error-correcting code Golay code

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Bounds on codes over an alphabet of five elements

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DISCRETE MATHEMATICS 2001年第1-3期240卷 13-19页

作者： Bogdanova, GT Östergård, PRJ Helsinki Univ Technol Dept Comp Sci & Engn Helsinki 02015 Finland Bulgarian Acad Sci Inst Math & Informat Veliko Tarnovo 5000 Bulgaria

We consider the problem of finding bounds and exact values of A(5)(n, d) - the maximum size of a code of length n and minimum distance d over an alphabet of 5 elements. Using a wide variety of constructions and methods, a table of bounds on A(5)(n, d) for n less than or equal to 11 is obtained. (C) 2001 Elsevier Science B.V. All rights reserved.

关键词： code construction error-correcting code q-ary code

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The Service Rate Region Polytope

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SIAM JOURNAL ON APPLIED ALGEBRA AND GEOMETRY 2024年第3期8卷 553-582页

作者： Alfarano, Gianira N. Kilic, Altan B. Ravagnani, Alberto Soljanin, Emina Eindhoven Univ Technol Eindhoven Netherlands Rutgers State Univ Piscataway NJ 08854 USA

We investigate the properties of a family of polytopes that naturally arise in connection with a problem in distributed data storage, namely service rate region polytopes. The service rate region of a distributed coded system describes the data access requests that the underlying system can support. In this paper, we study the polytope structure of the service rate region with the primary goal of describing its geometric shape and properties. We achieve this by introducing various structural parameters of the service rate region and establishing upper and lower bounds for them. The techniques we apply in this paper range from coding theory to optimization. One of our main results shows that every rational point of the service rate region has a so-called rational allocation, answering an open question in the research area.

关键词： service rate region polytope error-correcting code distributed data storage linear programming combinatorial geometry convex polytopes erasure-coded systems

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Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes

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MICROPROCESSORS AND MICROSYSTEMS 2014年第8期38卷 826-842页

作者： Zhang, Guangda Song, Wei Garside, Jim Navaridas, Javier Wang, Zhiying Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England Natl Univ Def Technol Sch Comp Changsha 410073 Hunan Peoples R China

Asynchronous circuit design is a promising technology for large-scale multi-core systems. As a family of asynchronous circuits, Quasi-delay-insensitive (QDI) circuits have been widely used to build chip-level long interconnects due to their tolerance to delay variations. However, QDI interconnects are vulnerable to faults. Traditional fault-tolerant techniques for synchronous circuits cannot be easily used to protect QDI interconnects. This paper focuses on protecting QDI interconnects from transient faults. The first contribution of this paper is a fault-tolerant delay-insensitive redundant check code named DIRC. Using DIRC in 4-phase 1-of-n QDI pipelines, all 1-bit and some multi-bit transient faults are tolerated. The DIRC and basic pipeline stages are mutually exchangeable. Arbitrary basic stages can be replaced by DIRC ones to strengthen fault-tolerance. This feature permits designers to use DIRC flexibly according to the practical design requirement. The second contribution is a redundant technique protecting the acknowledge wires (RPA). Experimental results indicate that DIRC pipelines have moderate area and speed overheads. Compared with unprotected basic pipelines, the average speed decrease of DIRC pipelines is less than 50%, with the 128-bit 1-of-2 DIRC pipeline only 28% slower. In severe environments with multi-bit transient faults, the fault-tolerance capability of DIRC pipelines increases thousands-fold. (C) 2014 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license.

关键词： Asynchronous circuits Quasi-delay-insensitive (QDI) interconnects Fault tolerance Transient fault 1-of-n error-correcting code

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A mixed upper bound on the maximum size of codes for multiple burst error correction and detection

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1998年第10期E81A卷 1964-1971页

作者： Hamada, M Univ Electrocommun Grad Sch Informat Syst Chofu Tokyo 1828585 Japan

We derive an upper bound on the size of a block code with prescribed burst-error-correcting capability combining those two ideas underlying the generalized Singleton and sphere-packing bounds. The two ideas are puncturing and sphere-packing. We use the burst metric defined by Gabidulin [1], which is suitable for burst error correction and detection. It is demonstrated that the proposed bound improves previously known ones for finite code-length, when minimum distance is greater than 3, as well as in the asymptotic forms.

关键词： error-correcting code burst error burst metric bound

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Biometric cryptosystem based on discretized fingerprint texture descriptors

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EXPERT SYSTEMS WITH APPLICATIONS 2013年第5期40卷 1888-1901页

作者： Imamverdiyev, Yadigar Teoh, Andrew Beng Jin Kim, Jaihie Yonsei Univ Biometr Engn Res Ctr Sch Elect & Elect Engn Seoul 120749 South Korea Inst Informat Technol ANAS Baku Azerbaijan

This paper focuses on a biometric cryptosystem implementation and evaluation based on a number of fingerprint texture descriptors. The texture descriptors, namely, the Gabor filter-based Fingercode, a local binary pattern (LBP), and a local direction pattern (LDP), and their various combinations are considered. These fingerprint texture descriptors are binarized using a biometric discretization method and used in a fuzzy commitment scheme (FCS). We constructed the biometric cryptosystems, which achieve a good performance, by fusing discretized fingerprint texture descriptors and using effective error-correcting codes. We tested the proposed system on a FVC2000 DB2a fingerprint database, and the results demonstrate that the new system significantly improves the performance of the FCS for texture-based fingerprints. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： Fuzzy commitment scheme Fingerprint texture descriptors Local binary pattern Biometric discretization error-correcting code

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DESIGN OF A FAULT-TOLERANT 3-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY WITH ON-CHIP error-correcting CIRCUIT

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IEEE TRANSACTIONS ON COMPUTERS 1993年第12期42卷 1453-1468页

作者： MAZUMDER, P Dept. of Electr. Eng. & Comput. Sci. Michigan Univ. Ann Arbor MI USA Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

As VLSI technology is inching forward to the ultimate limits of physical dimensions, memory manufacturers are striving to integrate more memory cells in a chip by employing innovative three-dimensional cell topographies. Most of the current-generation multimegabit dynamic random-access memory (DRAM) chips use three-dimensional storage capacitors where the charge is stored on a vertically integrated trench-type structure. It has been experimentally verified that these memory cells have poor reliability, because they are highly vulnerable to alpha particles, which frequently create plasma shorts between two adjoining trench capacitors on the same word line, resulting in uncorrectable double-bit soft errors. The conventional on-chip error-correcting codes (ECCs) cannot correct such double-bit/word-line soft errors. The paper presents a systematic study of soft-error related problems and it discusses the methodologies to correct single-bit and double-bit memory-cell upsets by using on-chip ECC circuits. Conventional double-error-correcting (DEC) codes used in digital communications are known to be inadequate for this application. By modifying the product code, an effective coding scheme has been designed in this paper that can be integrated within a DRAM chip to correct double-bit errors. The paper demonstrates that the reliability of a memory chip can be improved by several million times by integrating the proposed circuit. The area and timing overhead have been calculated and compared with the memory chips without any ECC and chips with single-error-correcting (SEC) codes. The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed by combinatorial enumeration.

关键词： AUGMENTED PRODUCT code DYNAMIC RANDOM-ACCESS MEMORY (DRAM) error-correcting code PROJECTIVE GEOMETRY code TRENCH CAPACITOR

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Binary codes for correcting Two Edits

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IEEE TRANSACTIONS ON INFORMATION THEORY 2024年第10期70卷 6877-6898页

作者： Sun, Yubo Ge, Gennian Capital Normal Univ Sch Math Sci Beijing 100048 Peoples R China

An edit refers to a single insertion, deletion, or substitution. This paper aims to construct binary codes that can correct two edits. To do this, a necessary and sufficient condition for a code to be two-edit correctable is provided, showing that a code is a two-edit correcting code if and only if it can correct two deletions, up to two substitutions, and one deletion and up to one substitution, separately. This criterion allows for the construction of two-edit correcting codes leveraging these three types of error correcting codes. In the field of constructing codes for correcting two deletions, we present a construction with 4 log n + O(log log n) redundant bits that can be viewed as a subcode proposed by Guruswami and Hastad, and provide an alternative proof. Moreover, our two-deletion correcting codes can also correct up to two substitutions after making a slight modification. In the field of constructing codes for correcting one deletion and up to one substitution, we present a construction with 4logn+O(log log n) redundant bits, which outperforms the best previously known results 6 log n + O(1) . Leveraging these codes, we obtain a construction of two-edit correcting codes with 6 log n + O(log log n) redundant bits. This outperforms the best previously known result, which requires at least 8 log n redundant bits. Moreover, we also consider the list-decoding problem under the two-edit channel and construct a two-edit list-decodable code with a list size of two employing 4 log n + O(log log n) redundant bits.

关键词： codes Transforms Germanium Termination of employment Task analysis Redundancy error correction codes Insertion deletion substitution edit error-correcting code list-decodable code

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Partial-sum queries in OLAP data cubes using covering codes

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IEEE TRANSACTIONS ON COMPUTERS 1998年第12期47卷 1326-1340页

作者： Ho, CT Bruck, J Agrawal, R IBM Corp Almaden Res Ctr San Jose CA 95120 USA CALTECH Pasadena CA 91125 USA

A partial-sum query obtains the summation over a set of specified cells of a data cube. We establish a connection between the covering problem in the theory of error-correcting codes and the partial-sum problem and use this connection to devise algorithms for the partial-sum problem with efficient space-time-trade-offs. For example,using our algorithms, with 44 percent additional storage, the query response time can be improved by about 12 percent;by roughly doubling the storage requirement, the query response time can be improved by about 34 percent.

关键词： partial-sum query covering code error-correcting code on-line analytical processing data cube multidimensional database precomputation query algorithm

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Optimal interleaving on tori

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SIAM JOURNAL ON DISCRETE MATHEMATICS 2006年第4期20卷 841-879页

作者： Jiang, Anxiao (Andrew) Cook, Matthew Bruck, Jehoshua Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA CALTECH Computat & Neural Syst Dept Pasadena CA 91125 USA CALTECH Dept Elect Engn Pasadena CA 91125 USA

This paper studies t- interleaving on two-dimensional tori. Interleaving has applications in distributed data storage and burst error correction, and is closely related to Lee metric codes. A t- interleaving of a graph is defined as a vertex coloring in which any connected subgraph of t or fewer vertices has a distinct color at every vertex. We say that a torus can be perfectly t- interleaved if its t- interleaving number ( the minimum number of colors needed for a t- interleaving) meets the sphere- packing lower bound, [t(2)/2]. We show that a torus is perfectly t-interleavable if and only if its dimensions are both multiples of t(2)+ 1/2 ( if t is odd) or t ( if t is even). The next natural question is how much bigger the t- interleaving number is for those tori that are not perfectly t-interleavable, and the most important contribution of this paper is to. nd an optimal interleaving for all *** large tori, proving that when a torus is large enough in both dimensions, its t- interleaving number is at most just one more than the sphere- packing lower bound. We also obtain bounds on t- interleaving numbers for the cases where one or both dimensions are not large, thus completing a general characterization of t- interleaving numbers for two-dimensional tori. Each of our upper bounds is accompanied by an efficient t-interleaving scheme that constructively achieves the bound.

关键词： bursts chromatic number cluster error-correcting code Lee distance multidimensional interleaving t-interleaving torus

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