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NOVEL MIXED codeS FOR MULTIPLE-CELL UPSETS MITIGATION IN STATIC RAMS

IEEE MICRO 2013年第6期33卷 66-74页

作者： Guo, Jing Xiao, Liyi Mao, Zhigang Zhao, Qiang Harbin Inst Technol Harbin Peoples R China Harbin Inst Technol Dept Elect Sci & Technol Harbin Peoples R China Harbin Inst Technol Ctr Microelect Harbin 150006 Peoples R China

Novel mixed codes (mcs) constructed from doubly transitive invariant (dti) and hamming codes are used to mitigate multiple-cell upsets (mcus) in common memories with lower overheads and higher code rates. The authors evaluate a double-error correction (dec) mc and compare it with existing dec codes, showing that the proposed mc can effectively mitigate mcus in memories and reduce the overheads of the extra circuits and memory cells.

关键词： doubly transitive invariant code error-correcting code multiple-cell upsets static RAM word length codes particle radiation code rate Hamming codes Memory Ham Upset Static random access storage

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correcting Deletions With Multiple Reads

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IEEE TRANSACTIONS ON INFORMATION THEORY 2022年第11期68卷 7141-7158页

作者： Chrisnata, Johan Kiah, Han Mao Yaakobi, Eitan Nanyang Technol Univ Sch Phys & Math Sci Singapore 637371 Singapore Technion Israel Inst Technol Dept Comp Sci IL-3200003 Haifa Israel

The sequence reconstruction problem, introduced by Levenshtein in 2001, considers a communication scenario where the sender transmits a codeword from some codebook and the receiver obtains multiple noisy reads of the codeword. Motivated by modern storage devices, we introduced a variant of the problem where the number of noisy reads N is fixed. Of significance, for the single-deletion channel, using log(2) log(2) n + O(1) redundant hits, we designed a reconstruction code of length n that reconstructs codewords from two distinct noisy reads (Cai et al., 2021). In this work, we show that log(2) log(2) n - O(1) redundant bits are necessary for such reconstruction codes, thereby, demonstrating the optimality of the construction. Furthermore, we show that these reconstruction codes can he used in t-deletion channels (with t >= 2) to uniquely reconstruct codewords from n(t-1)/(t - 1)! + O (n(t-2)) distinct noisy reads. For the two-deletion channel, using higher order VT syndromes and certain runlength constraints, we designed the class of higher order constrained shifted VT code with 2 log(2) n + O(log(2) (n)) redundancy bits that can reconstruct any codeword from any N >= 5 of its length-(n - 2) subsequences.

关键词： DNA-based data storage sequence reconstruction problem deletion channel error-correcting code multiple reads

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Facial Trait code

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2013年第4期23卷 648-660页

作者： Lee, Ping-Han Hsu, Gee-Sern Chen, Tsuhan Hung, Yi-Ping MediaTek Inc Hsinchu 30078 Taiwan Natl Taiwan Univ Sci & Technol Dept Mech Engn Taipei 106 Taiwan Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA Natl Taiwan Univ Grad Inst Networking & Multimedia Taipei 10617 Taiwan

We propose a facial trait code (FTC) to encode human facial images, and apply it to face recognition. Extracted from an exhaustive set of local patches cropped from a large stack of faces, the facial traits and the associated trait patterns can accurately capture the appearance of a given face. The extraction has two phases. The first phase is composed of clustering and boosting upon a training set of faces with neutral expression, even illumination, and frontal pose. The second phase focuses on the extraction of the facial trait patterns from the set of faces with variations in expression, illumination, and poses. To apply the FTC to face recognition, two types of codewords, hard and probabilistic, with different metrics for characterizing the facial trait patterns are proposed. The hard codeword offers a concise representation of a face, while the probabilistic codeword enables matching with better accuracy. Our experiments compare the proposed FTC to other algorithms on several public datasets, all showing promising results.

关键词： error-correcting code face recognition feature extraction

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Prediction of secondary protein structure with binary coding patterns of amino acid and nucleotide physicochemical properties

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INTERNATIONAL JOURNAL OF QUANTUM CHEMISTRY 2003年第2期92卷 123-134页

作者： Stambuk, N Konjevoda, P Rudjer Boskovic Inst HR-10002 Zagreb Croatia

We present binary coding algorithm for the alpha- and beta-protein fold prediction. The method links amino acid molecular polarity patterns and physicochemical properties of nucleotide bases coded by means of a binary addresses. Primary sequences that define secondary protein structure were analyzed with respect to the symbolic oligopeptides (SO) obtained bv the reduction of the 20 amino acid letter alphabet into a binary alphabet of nonpolar group 0 (W, C, I, F, M, V, L, Y) and polar group 1 (Q, R, H, K, N, E, D, S, G, T, A, P). The groups were extracted from the Grantham polarity scale with the clustering around medoids procedure. The transformation of protein strings into binary coding patterns of the polar and nonpolar amino acid groups reduced analyzed elements within the protein motif of length n by the factor of 10(n). SMO learning algorithm for the support vector machines was applied to classify alpha-helices and beta-strands. It was shown that the relative frequencies of binary hexapeptides classify all 174 nonhomologous alpha- and beta-protein folds from the Jpred database with 100%. accuracy. The results of 10-fold cross- validation and leave-one-out test were 86.78%. Classification tree confirmed the results of SMO analysis and correctly classified 100% of the folds by means of 9 binary hexapeptides. Linear block triple-check code was proposed for the description of hexapeptide patterns. The presented method enables simple, quick, and accurate prediction of alpha- and beta-protein folding types from the primary amino acid and nucleotide sequences on a personal computer. Our results imply that few amino acid polarity patterns specified by the nucleotide physicochemical properties describe basic protein folding types with >90% accuracy. (C) 2003 Wiley Periodicals, Inc.

关键词： protein fold secondary structure prediction error-correcting code genetic code nucleotides amino acids

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A Reconfigurable TDMP Decoder for Raptor codes

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第3期69卷 293-304页

作者： Zeineddine, Hady Mansour, Mohammad M. Amer Univ Beirut Beirut Lebanon

A Raptor code is a concatenation of a fixed rate precode and a Luby-Transform ( LT) code that can be used as a rateless error-correcting code over communication channels. By definition, Raptor codes are characterized by irregularity features such as dynamic rate, check-degree variability, and joint coding, which make the design of hardware-efficient decoders a challenging task. In this paper, serial turbo decoding of architecture-aware Raptor codes is mapped into sequential row processing of a regular matrix by using a combination of code enhancements and architectural optimizations. The proposed mapping approach is based on three basic steps: ( 1) applying systematic permutations on the source matrix of the Raptor code, ( 2) confining LT random encoding to pseudo-random permutation of messages and periodic selection of rowsplitting scenarios, and ( 3) developing a reconfigurable parallel check-node processor that attains a constant throughput while processing LT-and LDPC-nodes of varying degrees and count. The decoder scheduling is, thus, made simple and uniform across both LDPC and LT decoding. A serial decoder implementing the proposed approach was synthesized in 65 nm, 1.2 V CMOS technology. Hardware simulations show that the decoder, decoding a rate-0.4 code instance, achieves a throughput of 36 Mb/ s at SNR of 1.5 dB, dissipates an average power of 27 mW and occupies an area of 0.55 mm2.

关键词： Raptor codes Reconfigurable decoder error-correcting code Decoder architecture

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Existence condition for tail-biting convolutional codes

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IEICE TRANSACTIONS ON COMMUNICATIONS 2002年第11期E85B卷 2362-2368页

作者： Kim, Y Lee, PJ Pohang Univ Sci & Technol Div Elect & Comp Engn Pohang 790784 South Korea

We investigated the truncated convolutional code with the characteristics of a block code for block-based communication systems. Three truncation methods (direct truncation, tail-terminating, and tail-biting method) were introduced by other researchers. Each of the three methods has a weakness: the direct truncation method decreases the minimum distance, the tail-terminating method uses tail bits, and the tail-biting method can only be applied by using a complicated decoder, Although the tail-biting method gives a butter BER performance than the other two methods, we cannot apply the tail-biting method in all situations. Occasionally, the tail-biting convolutional code does not exist. Wang et al. presented two neccessary conditions for the existence of the tail-biting convolutional code of the rate-1/2 recursive systematic convolutional code. In this paper, we analyze the encoder of the convolutional code as a linear time invariant system, and present two theorems and six corollaries on the existence of the tail-biting convolutional code. These existence conditions are adaptable to all convolutional codes, In the communication system using the truncated convolutional code, these results are applicable to determining the truncation method.

关键词： convolutional code tail-biting code error-correcting code

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code RECOGNITION WITH NEURAL NETWORK DYNAMIC-SYSTEMS

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SIAM REVIEW 1990年第4期32卷 636-651页

作者： JEFFRIES, C Clemson Univ Clemson SC United States

A class of dynamical systems called neural networks can be used to solve a variety of finite choice problems including the problem of correcting binary code.

关键词： 68T20 68T10 neural network dynamical system error-correcting code content addressable memory

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A 100 pJ/bit, (32,8) CMOS Analog Low-Density Parity-Check Decoder Based on Margin Propagation

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2011年第6期46卷 1433-1442页

作者： Gu, Ming Chakrabartty, Shantanu Michigan State Univ Dept Elect & Comp Engn E Lansing MI 48824 USA

One of the key factors underlying the popularity of low-density parity-check (LDPC) code is its iterative decoding algorithm which is amenable to efficient analog and digital implementation. However, different applications of LDPC codes (e.g. wireless sensor networks) impose different sets of constraints which include speed, bit error rates (BER) and energy efficiency. Our previous work reported an algorithmic framework for designing margin propagation (MP) based LDPC decoders where the BER performance can be traded off with its energy efficiency. In this paper we present an analog current-mode implementation of an MP-based (32,8) LDPC decoder. The implementation uses only addition, subtraction and threshold operations and hence is independent of transistor biasing. Measured results from prototypes fabricated in a 0.5 mu m CMOS process verify the functionality of a (32,8) LDPC decoder and demonstrate the trade-off capability which is realized by adapting a system hyper-parameter. When configured as a min-sum LDPC decoder, the proposed implementation demonstrates superior BER performance compared to the state-of-the-art analog min-sum decoder at SNR greater than 3.5 dB. We show that an optimal configuration of the same MP-based decoder can also deliver up to 3 dB improvement in BER compared to the benchmark min-sum LDPC decoder.

关键词： Analog decoders current-mode circuits error-correcting code low-density parity-check (LDPC) decoder margin propagation (MP) piecewise-linear (PWL) approximation

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An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1997年第6期7卷 864-871页

作者： Hsu, JM Wang, CL Department of Electrical Engineering National Tsing Hua University Hsinchu Taiwan

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurring in the transmission process. Since the decoding profess for RS codes is rather computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for RS decoding. The architecture is developed based on a time-domain algorithm using the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clerk cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency.

关键词： error-correcting code pipelined architecture Reed-Solomon code Reed-Solomon decoder time-domain Berlekamp-Massey algorithm VLSI

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CONSTRUCTION OF SOME BINARY LINEAR codeS OF MINIMUM DISTANCE 5

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IEEE TRANSACTIONS ON INFORMATION THEORY 1991年第5期37卷 1429-1432页

作者： CHEN, CL IBM Corporation Poughkeepsie NY USA

A method of constructing binary linear codes is presented that have a minimum Hamming distance of five. Some efficient new codes are obtained. In particular, a (47,36,5) code is obtained that has six more information ... 详细信息

关键词： error-correcting code LINEAR BLOCK code

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