By using a run-length representation of sequences, ways to determine sub- and supersequences are discussed. This is then used in determining the number of sub- and supersequences of a sequence after double insertions ...
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By using a run-length representation of sequences, ways to determine sub- and supersequences are discussed. This is then used in determining the number of sub- and supersequences of a sequence after double insertions or deletions. It is also used in creating subsequence/supersequence books that are searched to find new double insertion/deletion correcting code books with higher cardinalities than those already known.
This letter extends a low-density parity-check code construction using maximum-length linear congruential sequences by Prabhakar and Narayanan. The corresponding bipartite graphs of their construction were guaranteed ...
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This letter extends a low-density parity-check code construction using maximum-length linear congruential sequences by Prabhakar and Narayanan. The corresponding bipartite graphs of their construction were guaranteed to have a girth larger than four by a sufficient condition. However, their sufficient condition was limited to regular codes and data-node degree equal to three. The extension in this letter allows arbitrary data-node degrees and is applicable to irregular codes. Further, simpler sufficient conditions are derived and larger girths are addressed.
Runlength-limited (RLL) codes are used in magnetic recording. The error patterns that occur with peak detection magnetic recording systems when using a runlength-limited code consist of both symmetric errors and shift...
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Runlength-limited (RLL) codes are used in magnetic recording. The error patterns that occur with peak detection magnetic recording systems when using a runlength-limited code consist of both symmetric errors and shift errors, We will refer to shift errors and symmetric errors collectively as mixed-type errors. In this correspondence, a method of providing error control for mixed-type errors that occur in a runlength-limited code comprised of(d, k) constrained sequences is examined. The coding scheme is to choose parity blocks to insert in the constrained information sequence. The parity blocks are chosen to satisfy the constraints and to provide some error control. The cases of single error detection and single errorcorrection are investigated, where the single error is allowed to be a shift error or a symmetric error. Bounds are discussed on the possible lengths for the parity blocks. It is shown that the single error-detection codes are the best possible in terms of the length of the parity blocks.
In this letter, we propose an efficient decoding algorithm for turbo product codes as introduced by Pyndiah. The proposed decoder has no performance degradation and reduces the complexity of the original decoder by an...
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In this letter, we propose an efficient decoding algorithm for turbo product codes as introduced by Pyndiah. The proposed decoder has no performance degradation and reduces the complexity of the original decoder by an order of magnitude. We concentrate on extended Bose-Chaudhuri-Hocquengem codes as the constituent row and column codes because of their already low implementation complexity. For these component codes, we observe that the weight and reliability factors can be fixed, and that there is no need for normalization. Furthermore, as opposed to previous efficient decoders, the newly proposed decoder naturally scales with a test-pattern parameter p that can change as a function of iteration number, i.e., the efficient Chase algorithm presented here uses conventionally ordered test patterns, and the syndromes, even parities, and extrinsic metrics are obtained with a minimum number of operations.
Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding...
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Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239;2) and (255, 231;3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders.
Asymptotic bounds are considered for unidirectional byte error-correcting codes. Upper bounds are developed from the concepts of the Singleton, Plotkin, and Hamming bounds. Lower bounds are also derived from a combina...
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Asymptotic bounds are considered for unidirectional byte error-correcting codes. Upper bounds are developed from the concepts of the Singleton, Plotkin, and Hamming bounds. Lower bounds are also derived from a combination of the generalized concatenated code construction and, the Varshamov-Gilbert bound. As the result, we find that there exist codes of low rate better than those on the basis of Hamming distance with respect to unidirectional byte error-correction.
A design of 4/6 intertrack-interference (ITI)-mitigating errorcorrection modulation code for bit-patterned media recording systems is proposed in this Letter. Generally, coding schemes in data storage devices are usu...
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A design of 4/6 intertrack-interference (ITI)-mitigating errorcorrection modulation code for bit-patterned media recording systems is proposed in this Letter. Generally, coding schemes in data storage devices are usually accomplished using a combination of error-correction coding and modulation coding. However, an interesting approach is that the modulation code itself has the capability of correcting errors. Such a modulation code design will reduce the total size and complexity of the data storage devices. In this Letter, the authors design a new 4/6 modulation code, where the code not only mitigates the effect of ITI but also maintains minimum Hamming distance of 2 to build up a trellis structure providing errorcorrection capability of the proposed code. Simulation results show that the proposed design outperforms prior arts. For instance, the performance of the proposed design is better than that of a conventional 4/6 modulation code about 8 dB at a bit error rate of 10(-7)under 20% read-head offtrack for the area density of 4 Tb/in(2).
We consider the problem of reliable communication over non-binary insertion/deletion channels where symbols are randomly deleted from or inserted in the received sequence and all symbols are corrupted by additive whit...
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We consider the problem of reliable communication over non-binary insertion/deletion channels where symbols are randomly deleted from or inserted in the received sequence and all symbols are corrupted by additive white Gaussian noise. To this end, we utilize the inherent redundancy achievable in non-binary symbol sets by first expanding the symbol set and then allocating part of the bits associated with each symbol to watermark symbols. The watermark sequence, known at the receiver, is then used by a forward-backward algorithm to provide soft information for an outer code which decodes the transmitted sequence. Through numerical results and discussions, we evaluate the performance of the proposed solution and show that it leads to significant system ability to detect and correct insertions/deletions. We also provide estimates of the maximum achievable information rates of the system, compare them with the available bounds, and construct practical codes capable of approaching these limits.
Rate adaptation is a technique that enables the selection of the most suitable error-correction coding rate according to the real-time channel quality, therefore increasing the overall throughput. We propose the use o...
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Rate adaptation is a technique that enables the selection of the most suitable error-correction coding rate according to the real-time channel quality, therefore increasing the overall throughput. We propose the use of rate adaptive convolutional codes for amplitude encoded, binary on-off keyed optical code-division multiple access (OCDMA) systems. Conventional OCDMA systems have a bit error probability floor due to optical multiple-user interference (OMUI). A convolutional coded OCDMA system (CC-OCDMA) lowers the error floors with increased coding rates but at the expense of reduced goodput (throughput minus the redundancy bits or symbols). However, by exploiting the variation of OMUI with user number, it is shown here that rate adaptation offers larger and consistent goodput improvements compared to fixed coding rate CC-OCDMA systems for various traffic profiles. This advantage is also observed in comparisons with OCDMA systems using improved receiver designs and 2D wavelength/time signatures codes. Based on the analytical results obtained here and the commercial availability of convolutional coding chipsets, rate-adaptive convolutional coding for OCDMA systems is worth to be considered for practical implementation. (C) 2004 Elsevier B.V. All rights reserved.
With the spread of Reed-Solomon (RS) codes to portable wireless applications, low-power RS decoder design has become important. This paper discusses how the Berlekamp Massey Decoding algorithm can be modified and mapp...
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With the spread of Reed-Solomon (RS) codes to portable wireless applications, low-power RS decoder design has become important. This paper discusses how the Berlekamp Massey Decoding algorithm can be modified and mapped to obtain a low-power architecture. In addition, architecture level modifications that speed-up the syndrome and error computations are proposed. Then the VLSI architecture and design of the proposed low-power/high-speed decoder is presented, The proposed design is compared with a normal design that does not use these algorithm/architecture modifications. The power reduction when compared to the normal design is estimated. The results indicate a power reduction of about 40% or a speed-up of 1,34.
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