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error-free strapdown inertial navigation system numerical updating algorithm in the launch-centered Earth-fixed frame for hypersonic vehicles

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AEROSPACE SCIENCE AND TECHNOLOGY 2023年 136卷

作者： Liu, Shangbo Pei, Sensen Ran, Zhiqiang Liang, Wenchao Chen, Kai Northwestern Polytech Univ Sch Elect & Informat Xian 710072 Peoples R China Northwestern Polytech Univ Sch Astronaut Xian 710072 Peoples R China

The two-sample numerical updating algorithm of strapdown inertial navigation systems (SINS) for hypersonic vehicles has a relatively large navigation error. To solve this problem, this paper proposes an error-free SINS numerical updating algorithm in the launch-centered Earth-fixed (LCEF) frame. First, the gyroscopes and accelerometers in SINS output angular increment and velocity increment respectively, while the proposed algorithm takes angular velocity and specific force as input, so the methods of angular increment fitting angular velocity and velocity increment fitting specific force are proposed. Then, according to the SINS differential equation in the LCEF frame, the error-free SINS numerical updating algorithm in the LCEF frame is designed by adopting the Taylor series expansion method. The derivation process of the algorithm shows that the proposed algorithm can achieve precise compensation for the non-exchangeable errors of attitude, velocity, and position, and selecting the LCEF frame as the navigation frame has greater advantages than the local-level frame. Finally, two-sample and error-free numerical updating algorithms are simulated and compared by taking the hypersonic boost-gliding vehicle as the object. Under the influence of a pure SINS algorithm, the velocity error of the two-sample algorithm with a simulation duration of 1100 s is in the order of 10-2 m/s, and the position error is in the order of 10 m. In contrast, the velocity error of the proposed algorithm is in the order of 10-7 m/s, and its position error is in the order of 10-4 m. (c) 2023 Elsevier Masson SAS. All rights reserved.

关键词： Hypersonic vehicle Launch-centered Earth-fixed frame Strapdown inertial navigation system Numerical updating algorithm error-free algorithm

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Two Level 2-DDWT Convolution Structure for High Speed Operation using Daubehies Wavelet 1

Two Level 2-DDWT Convolution Structure for High Speed Operat...

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IEEE International Conference on Electrical, Computer and Communication Technologies

作者： Kanth, V. Krushna Samundiswary, P. Pondicherry Univ Dept Elect Engn Pondicherry India

ISBN: (纸本)9781479960859

The Discrete Wavelet Transform (DWT) has a huge number of applications in science and engineering technology. It is used for signal coding, to represent a discrete signal in a more redundant form, often as a preconditioning for data compression. Practical applications can also be found in signal processing, digital communications and many others. There are several techniques available for DWT like orthogonal, bi-orthogonal, HAAR, Dual-Tree Complex Wavelet Transform, and Newland transform. A multiplier-less based architecture on algebraic integer representation for computing the Daubechies6-tap wavelet transform is used for two level 2D-DWT as wavelet filters in image processing. This architecture improves on previous designs in a way that it minimizes the number of parallel 2-input adder circuits. In this paper the design is implemented for a two-level 2-D decomposition using a Xilinx Virtex-6 xc6vcx75t-2-ff484 field programmable gate array (FPGA) device operating at up to a maximum clock frequency of 344/168 MHz.

关键词： Algebraic integer encoding bi-orthogonal Daubechies wavelets error-free algorithm orthogonal subband coding

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Algebraic integer architecture with minimum adder count for the 2-D Daubechies 4-tap filters banks

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MULTIDIMENSIONAL SYSTEMS AND SIGNAL PROCESSING 2014年第4期25卷 829-845页

作者： Madishetty, Shiva K. Madanayake, Arjuna Cintra, Renato J. Dimitrov, Vassil S. Mugler, Dale H. Univ Akron Dept Elect & Comp Engn Akron OH 44325 USA Univ Fed Pernambuco Signal Proc Grp Dept Estat Recife PE Brazil Univ Calgary Dept Elect & Comp Engn Calgary AB Canada Univ Akron Dept Biomed Engn Akron OH 44325 USA

A multiplierless architecture based on algebraic integer representation for computing the Daubechies 4-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using numerical optimization based o exhaustive search over the algebraic integer representation. The proposed architecture furnishes exact computation up to the final reconstruction step, which is the operation that maps the exactly computed filtered results from algebraic integer representation to fixed-point. Compared to Madishetty et al. (IEEE Trans Circuits Syst I (Accepted, In Press), 2012a), this architecture shows a reduction of adder circuits, where is the number of wavelet decomposition levels. Standard images Mandrill, Lena, and Cameraman were submitted to digital realizations of both proposed algebraic integer based as well as fixed-point schemes, leading to quantifiable comparisons. The design is physically implemented for a 4-level 2-D decomposition using a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device operating at up to a maximum clock frequency of 263.15 MHz. The FPGA implementation is tested using hardware co-simulation using an ML605 board with clock of 100 MHz. A 45 nm CMOS synthesis shows improved clock frequency of better than 500 MHz for a supply voltage of 1.1 V.

关键词： Algebraic integer encoding Daubechies wavelets error-free algorithm Subband coding

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Precise VLSI Architecture for AI Based 1-D/2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2014年第7期61卷 1984-1993页

作者： Madishetty, Shiva K. Madanayake, Arjuna Cintra, Renato J. Dimitrov, Vassil S. Univ Akron Dept Elect & Comp Engn Akron OH 44325 USA Univ Fed Pernambuco Dept Estat Signal Proc Grp Recife PE Brazil Univ Calgary Dept Elect & Comp Engn Calgary AB Canada

A multiplier-less architecture based on algebraic integer representation for computing the Daubechies 6-tap wavelet transform for 1-D/ 2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using brute-force numerical optimization of the algebraic integer representation. The proposed architecture furnishes exact computation up to the final reconstruction step, which is the operation that maps the exactly computed filtered results from algebraic integer representation to fixed-point. Compared to our recent work, this architecture shows a reduction of 27 . n - 16 adder circuits, where n is the number of wavelet decomposition levels. The design is physically implemented for a 4-level 1-D/ 2-D decomposition using a Xilinx Virtex-6 vcx240t-1ff1156 field programmable gate array (FPGA) device operating at up to a maximum clock frequency of 344/ 168 MHz. The FPGA implementation of 1-D/ 2-D are tested using hardware co-simulation using an ML605 board with clock of 100 MHz. A 45 nm CMOS synthesis of 2-D designs show improved clock frequency of better than 306 MHz for a supply voltage of 1.1 V.

关键词： Algebraic integer encoding Daubechies wavelets error-free algorithm subband coding

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VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2013年第6期60卷 1455-1468页

作者： Madishetty, Shiva Kumar Madanayake, Arjuna Cintra, Renato J. Dimitrov, Vassil S. Mugler, Dale H. Univ Akron Dept Elect & Comp Engn Akron OH 44325 USA Univ Fed Pernambuco Dept Estat Signal Proc Grp BR-50670901 Recife PE Brazil Univ Calgary Dept Elect & Comp Engn Calgary AB T2N 1N4 Canada Univ Akron Dept Biomed Engn & Appl Math Akron OH 44325 USA

This paper proposes a novel algebraic integer (AI) based multi-encoding of Daubechies-4 and -6 2-D wavelet filters having error-free integer-based computation. Digital VLSI architectures employing parallel channels are proposed, physically realized and tested. The multi-encoded AI framework allows a multiplication-free and computationally accurate architecture. It also guarantees a noise-free computation throughput the multi-level multi-rate 2-D filtering operation. A single final reconstruction step (FRS) furnishes filtered and down-sampled image outputs in fixed-point, resulting in low levels of quantization noise. Comparisons are provided between Daubechies-4 and -6 designs in terms of SNR, PSNR, hardware structure, and power consumptions, for different word lengths. SNR and PSNR improvements of approximately 30% were observed in favour of AI-based systems, when compared to 8-bit fixed-point schemes (six fractional bits). Further, FRS designs based on canonical signed digit representation and on expansion factors are proposed. The Daubechies-4 and -6 4-level VLSI architectures are prototyped on a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device at 282 MHz and 146 MHz, respectively, with dynamic power consumption of 164 mW and 339 mW, respectively, and verified on FPGA chip using an ML605 platform.

关键词： Algebraic integer encoding Daubechies wavelets error-free algorithm fixed-point scheme sub-band coding VLSI

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error-free VLSI Architecture for the 2-D Daubechies 4-tap Filter using Algebraic Integers

Error-free VLSI Architecture for the 2-D Daubechies 4-tap Fi...

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IEEE International Symposium on Circuits and Systems

作者： Madishetty, Shiva Madanayake, Arjuna Cintra, Renato J. Mugler, Dale Dimitrov, Vassil S. Univ Akron ECE Akron OH 44325 USA

ISBN: (纸本)9781467302197

In this paper, a multi-encoding approach using wavelet based subband coding is proposed to accomplish error free calculations from exact representation of Daubechies 4-tap wavelet filter coefficients using the algebraic integer (AI) representation. By mapping the irrational coefficients to a convenient AI basis, the proposed architecture is designed employing a parallel channel model having two data paths carrying integer sequences. The computations done in the AI architecture are exactly accurate and are done entirely in a multiplier-free circuit. The design is implemented on a Xilinx Virtex-6 device at 172 MHz and hardware co-simulated with an ML605 board at 100 MHz. AI mapping facilitates simplicity and error-free calculations. The proposed architecture has a single final reconstruction step (FRS). Booth encoding has been adopted at the FRS to minimize the error which can be incurred at this point. This paper provides a hardware and power analysis for different bit lengths. An example output image sequence for the mandrill image is also provided.

关键词： Algebraic integer encoding Daubechies wavelets error-free algorithm subband coding

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Corrections to 'Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping'

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2012年第8期59卷 511-514页

作者： Lai, Shin-Chi Yeh, Yi-Ping Lei, Sheau-Fang Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

Islam and Wahid proposed an area-and power-efficient design of Daubechies wavelet transforms. However, it was found that the matrix decompositions of the folded algebraic-integer-quantization scheme for DAUB4 and DAUB6 are incorrect and do not correspond with their architecture designs. We propose modifications not only to the algorithm but also to its implementation. Compared with the original method, the proposed design requires fewer adders and maintains the same critical path.

关键词： Algebraic integer quantization (AIQ) Daubechies wavelet error-free algorithm folded mapping

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Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2010年第9期57卷 716-720页

作者： Islam, Md. Ashraful Wahid, Khan A. Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK S7N 5A9 Canada

In this brief, we present an efficient design of a shared architecture to compute two 8-point Daubechies wavelet transforms. The architecture is based on a two-level folded mapping technique that is developed on the factorization and decomposition of transform matrices exploiting the symmetrical structure. The chip occupies a 2.08-mm(2) silicon area, runs at 100 MHz, and consumes 4.51 mW of power in 0.18-mu m CMOS technology.

关键词： Algebraic integer quantization (AIQ) Daubechies wavelet error-free algorithm folded mapping

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An iterative error-free algorithm to solve Vandermonde systems

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APPLIED MATHEMATICS AND COMPUTATION 2001年第1期117卷 45-54页

作者： Morhác, M Slovak Acad Sci Inst Phys Bratislava 84228 Slovakia

The paper describes an algorithm to solve Vandermonde system of linear equations. The algorithm is error-free, i.e., it does not introduce either rounding-off errors or errors caused by finite length of computer word into the solution. Cost analysis and its comparison to alternative error-free method are included. (C) 2001 Elsevier Science Inc. All rights reserved.

关键词： vandermonde system error-free algorithm rounding-off errors cost analysis linear equations

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