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execution-driven simulation of multiprocessors. Address and timing analysis

ACM Transactions on Modeling and Computer simulation 1994年第4期4卷 314-314页

作者： Dwarkadas, S. Jump, J.R. Sinclair, J.B. Rice University Rice University Rice University

This article describes and evaluates an efficient execution-driven technique for the simulation of multiprocessors that includes the simulation of system memory and that is driven by real program work loads. The technique produces correctly interleaved address traces at run-time without disk access overhead or hardware support, allowing accurate simulation of the effects of a variety of architectural alternatives on programs. We have implemented a simulator based on this technique that offers substantial advantages in terms of reduced time and space overheads when compared to instruction-driven or trace-driven simulation techniques, without significant loss of accuracy. The article presents the results of several validation experiments used to quantify the accuracy and efficiency of the simulator for sequential, distributed, and shared-memory multiprocessors, and several parallel programs. These experiments show that prediction errors of less than 5 percent as compared to actual execution times, and overheads 6 to 30 times lower than those incurred by cycle-level simulation can be achieved. Predictions of relative performance metrics such as speedup tend to be even more accurate, making this technique especially attractive as an efficient method for comparative investigations of parallel system designs.

关键词： distributed systems execution-driven simulation parallel tracing shared-memory multiprocessors

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PS-SIM: An execution-driven Performance simulation Technology Based on Process-Switch

PS-SIM: An Execution-Driven Performance Simulation Technolog...

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International Conference on Advances in Computer Science, Environment, Ecoinformatics, and Education

作者： Guo, Xiaowei Lin, Yufei Xu, Xinhai Zhang, Xin National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)9783642233234

Nowadays, the performance of large-scale parallel computer system improves continuously, and the system scale becomes extremely large. Performance prediction has become an important approach to guide system design, implementation and optimization. simulation method is the most widely used performance prediction technology for large-scale parallel computer system. In this paper, after analyzing the extant problems, we proposed a novel execution-driven performance simulation technology based on process-switch. We designed a simulation framework named PS-SIM, and implemented a prototype system based on MPICH2. Finally, we verified the proposed approach by experiments. Experimental results show that the approach has high accuracy and simulation performance.

关键词： Performance Prediction Large-Scale Parallel Computer System execution-driven simulation MPICH

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Design Space Exploration of an execution-driven Functional simulation Methodology 31

Design Space Exploration of an Execution-Driven Functional S...

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31st International Conference on VLSI Design / 17th International Conference on Embedded Systems (VLSID & ES))

作者： Mahapatra, Ipsita Biswas Agarwal, Utkarsh Azad, Chandrashekhar Nandy, S. K. Indian Inst Sci Ctr Nano Sci & Engn Bangalore 560012 Karnataka India Adobe Syst Bangalore 560012 Karnataka India Bhagalpur Coll Engn Bhagalpur 813210 India Indian Inst Sci Deparment Computat & Data Sci Bangalore 560012 Karnataka India

ISBN: (纸本)9781538636923

Exploration of an efficient functional simulation methodology that has the capability to encounter conflicting conditions such as: maximizing hardware occupancy using efficient partitioning and mapping algorithms and minimizing inter hardware communication using optimized hardware dimensions, is very important. In this paper, we explore the design space of an execution-driven functional simulation methodology named EX-DRIVE. It performs functional simulation of a design under test (DUT) without the need for hardware synthesis and implementation of the DUT, offering significant improvement in functional simulation time. To realize this methodology we use a Network of Interconnected HyperCells (NIHC) as the meta platform. We explore the design space of EX-DRIVE for various dimensions of NIHC fabric and different partitioning and mapping algorithms. For this study we investigate six different hardware dimensions having a fixed hardware capacity and three partitioning and mapping algorithms: a Discrete Particle Swarm Optimization based algorithm (DPSO), a heuristic and a convex algorithm. We find that, for a fixed hardware capacity, the heuristic and convex algorithm proves to be more efficient for large and densely connected DUTs whereas the DPSO based algorithm proves to be more efficient for smaller and sparsely connected data flow graphs. The proposed algorithms are generic enough to be applied to any coarse grained re-configurable array assisted functional simulation platform.

关键词： VLSI Functional simulation execution-driven simulation Re-configurable hardware

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An efficient tree cache coherence protocol for distributed shared memory multiprocessors

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IEEE TRANSACTIONS ON COMPUTERS 1999年第3期48卷 352-360页

作者： Chang, YK Bhuyan, LN Chung Hua Univ Dept Informat Management Hsinchu 30067 Taiwan Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA

Directory schemes have long been used to solve the cache coherence problem for large scale shared memory multiprocessors. In addition, tree-based protocols have been employed to reduce the directory size and the invalidation latency for a large degree of data sharing in the system. However, the existing tree-based protocols involve a very high communication overhead for maintaining a balanced tree, especially when the degree of data sharing is low. This paper presents a new tree-based cache coherence protocol which is a hybrid of the limited directory and the linked list schemes. By utilizing a limited number of pointers in the directory, the proposed protocol connects the nodes caching a shared block in a tree fashion without incurring any communication overhead. In addition to the low communication overhead. the proposed scheme also possesses the advantages of the existing bit-map and tree-based linked list protocols, namely, scalable memory requirement and logarithmic invalidation latency. We evaluate the performance of our protocol by running four applications on the Proteus execution-driven simulator. Our simulation results show that the performance of the proposed protocol is very close to that of the full-map protocol.

关键词： cache coherence tree-based directory protocols shared memory large scale multiprocessors execution-driven simulation

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Switch MSHR: A technique to reduce remote read memory access time in CC-NUMA multiprocessors

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IEEE TRANSACTIONS ON COMPUTERS 2003年第5期52卷 617-632页

作者： Bhuyan, LN Wang, HJ Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA

A remote memory access poses a severe problem for the design of CC-NUMA multiprocessors because it takes an order of magnitude longer than the local memory access. The large latency arises partly due to the increased distance between the processor and remote memory over the interconnection network. In this paper, we develop a new switch architecture, called Switch MSHR (SMSHR), which provides the cache block to the requesting processors without those requests having to go to the home memory, The SMSHR idea is based on providing a few miss status holding registers (MSHRs) in each switch that keep track of read requests to the memory. The SMSHR blocks secondary requests to the same memory block and provides them with a copy of the block when the primary reply returns. The SMSHR design is then extended to include a switch cache, which can temporarily save a copy of the data block for later use. We provide basic block designs for the SMSHR and SMSHR+cache architectures in this paper. We explore the design space by modeling the new switch architectures in a detailed execution-driven simulator and analyze the performance benefits. Our simulation results show that applications with a high degree of data sharing benefit tremendously from the SMSHR and SMSHR+cache techniques.

关键词： CC-NUMA multiprocessor memory latency problem interconnection network miss status holding register execution-driven simulation

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An application-driven study of parallel system overheads and network bandwidth requirements

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1999年第3期10卷 193-210页

作者： Sivasubramaniam, A Singla, A Ramachandran, U Venkateswaran, H Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA Silicon Graph Inc Mt View CA USA Georgia Inst Technol Coll Comp Atlanta GA 30332 USA

Evaluating and analyzing the performance of a parallel application on an architecture to explain the disparity between projected and delivered performance is an important aspect of parallel systems research. However, conducting such a study is hard due to the vast design space of these systems. In this paper, we study two important aspects related to the performance of parallel applications on shared memory parallel architectures. First, we quantify overheads observed during the execution of these applications on three different simulated architectures. We next use these results to synthesize the bandwidth requirements for the applications with respect to different network topologies. This study is performed using an execution-driven simulation tool called SPASM, which provides a way of isolating and quantifying the different parallel system overheads in a nonintrusive manner. The first exercise shows that in shared memory machines with private caches, as long as the applications are well-structured to exploit locality, the key determinant that impacts performance is network connection. The second exercise quantifies the network bandwidth needed to minimize the effect of network connection. specifically, it is shown that for the applications considered, as long as the problem sizes are increased commensurate with the system size, current network technologies supporting 200-300 MBytes/sec link bandwidth are sufficient to keep the network overheads (such as latency and contention) within acceptable bounds.

关键词： parallel systems overheads execution-driven simulation interconnection network application-driven study

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Design and evaluation of a switch cache architecture for CC-NUMA multiprocessors

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IEEE TRANSACTIONS ON COMPUTERS 2000年第8期49卷 779-797页

作者： Iyer, RR Bhuyan, LN Intel Corp Beaverton OR 97006 USA Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA

Cache coherent nonuniform memory access (CC-NUMA) multiprocessors provide a scalable design for shared memory. But, they continue to suffer from large remote memory access latencies due to comparatively slow memory technology and large data transfer latencies in the interconnection network. In this paper, we propose a novel hardware caching technique, called switch cache, to improve the remote memory access performance of CC-NUMA multiprocessors. The main idea is to implement small fast caches in crossbar switches of the interconnect medium to capture and store shared data as they flow from the memory module to the requesting processor. This stored data acts as a cache for subsequent requests, thus reducing the need for remote memory accesses tremendously. The implementation of a cache in a crossbar switch needs to be efficient and robust, yet flexible for changes in the caching protocol. The design and implementation details of a CAche Embedded Switch ARchitecture, CAESAR, using wormhole routing with Virtual channels is presented. We explore the design space of switch caches by modeling CAESAR in a detailed execution driven simulator and analyze the performance benefits. Our results show that the CAESAR switch cache is capable of improving the performance of CC-NUMA multiprocessors by up to 45 percent reduction in remote memory accesses for some applications. By serving remote read requests at various stages in the interconnect, we observe improvements in execution time as high as 20 percent for these applications. We conclude that switch caches provide a cost-effective solution for designing high performance CC-NUMA multiprocessors.

关键词： crossbar switches cache architectures scalable interconnects wormhole routing shared memory multiprocessors execution-driven simulation

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A comparative evaluation of hybrid distributed shared-memory systems

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JOURNAL OF SYSTEMS ARCHITECTURE 2009年第1期55卷 43-52页

作者： Moga, Adrian Dubois, Michel Univ So Calif Dept Elect Engn Los Angeles CA 90089 USA Intel Corp Hillsboro OR 97124 USA

Distributed Shared-Memory (DSM) systems are shared-memory multiprocessor architectures in which each processor node contains a partition of the shared memory. In hybrid DSM systems coherence among caches is maintained by a software-implemented coherence protocol relying on some hardware support. Hardware support is provided to satisfy every node hit (the common case) and software is invoked only for accesses to remote nodes. In this paper we compare the design and performance of four hybrid distributed shared memory (DSM) organizations by detailed simulation of the same hardware platform. We have implemented the software protocol handlers for the four architectures. The handlers are written in C and assembly code. Coherence transactions are executed in trap and interrupt handlers. Together with the application, the handlers are executed in full detail in execution-driven simulations of six complete benchmarks with coarse-grain and fine-grain sharing. We relate our experience implementing and simulating the software protocols for the four architectures. Because the overhead of remote accesses is very high in hybrid systems, the system of choice is different than for purely hardware systems. (c) 2008 Elsevier B.V. All rights reserved.

关键词： Distributed shared memory Multiprocessor systems NUMA Software cache coherence execution-driven simulation

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Toward a more realistic performance evaluation of interconnection networks

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1997年第7期8卷 681-694页

作者： Ligon, WB Ramachandran, U GEORGIA INST TECHNOL COLL COMPATLANTAGA 30332

Interconnection network design plays a central role in the design of parallel systems. Most of the previous research has evaluated the performance of interconnection networks in isolation. in this study, we investigate the relationship between application program characteristics and interconnection network performance using an execution driven simulation testbed: the Reconfigurable Architecture Workbench (RAW). We simulate five topological configurations of a k-ary n-cube interconnect and four different network [ink models for a 4,096 node SIMD machine, and quantify the impact of the network on two application programs. We provide experimental evidence that such ''in-context'' simulation provides a better view of the impact of network design Variables on system performance. We show that recent results, indicating that low-dimensional designs provide better ICN performance, ignore application requirements that may favor high-dimensional designs. Furthermore, applications that would appear to favor low-dimensional designs may not, in fact, be significantly impacted by the network's dimensionality. We experimentally test the results of published performance models comparing the use of a synthetic load to that of a toad generated by a typical application program. The experiments indicate that the standard metric of average message latency can vary considerably under different application loads and that average message latency may not reflect overall application performance. In particular, at the level of the offered (application generated) load to the network, the topological properties of the network are important in determining the average message latency. However, for overall application performance, we found that the network topology may not be critical so long as there is sufficient network bandwidth. in such cases, the results suggest that optimizing the implementation cost of the network should be the key design criterion. We also present a simple abstraction for

关键词： interconnection networks parallel systems performance evaluation execution-driven simulation application-directed study image understanding algorithms

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Improving the accuracy of history-based branch prediction

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IEEE TRANSACTIONS ON COMPUTERS 1997年第4期46卷 469-472页

作者： Kaeli, DR Emma, PG IBM CORP THOMAS J WATSON RES CTRYORKTOWN HTSNY 10598

In this paper, we present mechanisms that improve the accuracy and performance of history-based branch prediction. By studying the characteristics of the decision structures present in high-level languages, two mechanisms are proposed that reduce the number of wrong predictions made by a branch target buffer (BTB). execution-driven modeling is used to evaluate the improvement in branch prediction accuracy, as well as the reduction in overall program execution.

关键词： history-based branch prediction BTB high-level language execution-driven simulation call/return stack case block table

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