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A fast Cartesian Grid-Based Integral Equation Method for Unbounded Interface Problems with Non-Homogeneous Source Terms

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Communications in Computational Physics 2023年第6期33卷 208-234页

作者： Jiahe Yang Wenjun Ying School of Mathematical Sciences Shanghai Jiao Tong UniversityMinhangShanghai 200240P.R.China Department of Mathematics MOE-LSC and Institute of Natural SciencesShanghai Jiao Tong UniversityMinhangShanghai 200240P.R.China

This work presents a fast Cartesian grid-based integral equation method for unbounded interface problems with non-homogeneous source *** unbounded interface problem is solved with boundary integral equation methods such that infinite boundary conditions are satisfied *** work overcomes two *** first difficulty is the evaluation of singular *** and volume integrals are transformed into equivalent but much simpler bounded interface problems on rectangular domains,which are solved with FFT-based finite difference *** second one is the expensive computational cost for volume *** the use of efficient interface problem solvers,the evaluation for volume integrals is still expensive due to the evaluation of boundary conditions for the simple interface *** problem is alleviated by introducing an auxiliary circle as a bridge to indirectly evaluate boundary *** solving boundary integral equations on a circular boundary is so accurate,one only needs to select a fixed number of points for the discretization of the circle to reduce the computational *** examples are presented to demonstrate the efficiency and the second-order accuracy of the proposed numerical method.

关键词： Interface problem unbounded domain boundary integral equation kernel-free method auxiliary circle Cartesian grid method fast algorithm

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fast Control for Backlight Power-Saving algorithm Using Motion Vectors from the Decoded Video Stream

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SENSORS 2022年第19期22卷 7170页

作者： Chen, Shih-Lun Chen, Tsung-Yi Lin, Ting-Lan Chen, Chiung-An Lin, Szu-Yin Chiang, Yu-Liang Tung, Kun-Hsien Chiang, Wei-Yuan Chung Yuan Christian Univ Dept Elect Engn Chungli 32023 Taiwan Natl Taipei Univ Technol Dept Elect Engn Taipei 10608 Taiwan Ming Chi Univ Technol Dept Elect Engn New Taipei 24301 Taiwan Natl Ilan Univ Dept Comp Sci & Informat Engn Yilan 26047 Taiwan Natl Synchrotron Radiat Res Ctr Hsinchu 30076 Taiwan

Backlight power-saving algorithms can reduce the power consumption of the display by adjusting the frame pixels with optimal clipping points under some tradeoff criteria. However, the computation for the selected clipping points can be complex. In this paper, a novel algorithm is created to reduce the computation time of the state-of-the-art backlight power-saving algorithms. If the current frame is similar to the previous frame, it is unnecessary to execute the backlight powersaving algorithm for the optimal clipping points, and the derived clipping point from the previous frame can be used for the current frame automatically. In this paper, the motion vector information was used as the measurement of the similarity between adjacent frames, where the generation of the motion vector information requires no extra complexity since it is generated to reconstruct the decoded frame pixels before the display. The experiments showed that the proposed work can reduce the running time of the state-of-the-art methods by 25.21% to 64.22%, while the performances are maintained;the differences with the state-of-the-art methods in PSNR are only 0.02 similar to 1.91 dB, and those in power are only -0.001 similar to 0.008 W.

关键词： LCD (liquid crystal display) motion vectors backlight power-saving fast algorithm

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Evaluating fast algorithms for Convolutional Neural Networks on FPGAs

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第4期39卷 857-870页

作者： Liang, Yun Lu, Liqiang Xiao, Qingcheng Yan, Shengen Peking Univ Sch EECS Beijing 100871 Peoples R China Peng Cheng Lab Shenzhen 518055 Peoples R China Peking Univ Ctr Energy Efficient Comp & Applicat Beijing 100871 Peoples R China SenseTime Algorithm Platform Dept Hong Kong Peoples R China

In recent years, convolutional neural networks (CNNs) have become widely adopted for computer vision tasks. Field-programmable gate arrays (FPGAs) have been adequately explored as a promising hardware accelerator for CNNs due to its high performance, energy efficiency, and reconfigurability. However, prior FPGA solutions based on the conventional convolutional algorithm is often bounded by the computational capability of FPGAs (e.g., the number of DSPs). To address this problem, the feature maps are transformed to a special domain using fast algorithms to reduce the arithmetic complexity. Winograd and fast Fourier transformation (FFT), as fast algorithm representatives, first transform input data and filter to Winograd or frequency domain, then perform element-wise multiplication, and apply inverse transformation to get the final output. In this paper, we propose a novel architecture for implementing fast algorithms on FPGAs. Our design employs line buffer structure to effectively reuse the feature map data among different tiles. We also effectively pipeline the Winograd/FFT processing element (PE) engine and initiate multiple PEs through parallelization. Meanwhile, there exists a complex design space to explore. We propose an analytical model to predict the resource usage and the performance. Then, we use the model to guide a fast design space exploration. Experiments using the state-of-the-art CNNs demonstrate the best performance and energy efficiency on FPGAs. We achieve 854.6 and 2479.6 GOP/s for AlexNet and VGG16 on Xilinx ZCU102 platform using Winograd. We achieve 130.4 GOP/s for Resnet using Winograd and 201.1 GOP/s for YOLO using FFT on Xilinx ZC706 platform.

关键词： Field programmable gate arrays Convolution Space exploration Prediction algorithms Transforms Analytical models Convolutional neural networks Convolutional neural network (CNN) fast algorithm fast Fourier transformation (FFT) field-programmable gate array (FPGA) Winograd

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Generalization of the fast Fourier Transform with a Constant Structure

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COMPUTATIONAL MATHEMATICS AND MATHEMATICAL PHYSICS 2023年第8期63卷 1371-1380页

作者： Bespalov, M. S. Vladimir State Univ Vladimir 600000 Russia

The widely popular famous fast Cooley-Tukey algorithms for the discrete Fourier transform of mixed radix are presented in two forms: classical and with a constant structure. A matrix representation of these algorithms is proposed in terms of two types of tensor product of matrices: the Kronecker product and the b-product. This matrix representation shows that the structure of these algorithms is identical to two fast Good algorithms for a Kronecker power of a matrix. A technique for constructing matrix-form fast algorithms for the discrete Fourier and Chrestenson transforms with mixed radix and for the discrete Vilenkin transform is demonstrated. It is shown that the constant-structured algorithm is preferable in the case of more sophisticated constructions.

关键词： discrete Fourier transform discrete Walsh transform fast algorithm Kronecker product of matrices

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A fast CU size decision algorithm for VVC intra prediction based on support vector machine

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MULTIMEDIA TOOLS AND APPLICATIONS 2020年第37-38期79卷 27923-27939页

作者： Chen, Fen Ren, Yan Peng, Zongju Jiang, Gangyi Cui, Xin Chongqing Univ Technol Sch Elect & Elect Engn Chongqing 400054 Peoples R China Ningbo Univ Fac Informat Sci & Engn Ningbo 315211 Zhejiang Peoples R China

The latest generation of coding standard, Versatile Video Coding (VVC), has achieved more bitrate reduction compared with high efficiency video coding. However, the introduction of quadtree with nested Multi-Type Tree (MTT) coding structure greatly increases the computational complexity. To reduce the complexity of VVC, a Support Vector Machine (SVM) based Coding Unit (CU) size decision algorithm is presented. Firstly, effective features, derived from entropy, texture contrast, and Haar wavelet efficient of current CU, are select to distinguish the splitting directions. Then, the six SVM classifying models are on-line trained at different CU sizes. Finally, the models are utilized to prediction the direction of CU splitting in the quadtree with nested MTT coding structure. Experimental results show that the proposed algorithm can significantly save the encoding time by 51.01% with slight increase of Bjontegaard delta bit rate.

关键词： Versatile video coding fast algorithm Support vector machine CU splitting

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A fast accurate artificial boundary condition for the Euler-Bernoulli beam

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NUMERICAL algorithmS 2023年第4期93卷 1685-1718页

作者： Zheng, Zijun Pang, Gang Chongqing Univ Technol Chongqing 400054 Peoples R China Beihang Univ Sch Math Sci Beijing 102206 Peoples R China

It is difficult to convert the PDEs defined on the whole space with higher order space derivatives into initial boundary value problems by proposing boundary conditions. In this paper, we use an absorbing boundary condition method to solve the Cauchy problem for one-dimensional Euler-Bernoulli beam with fast convolution boundary condition which is derived through the Pade approximation for the square root function root center dot. We also introduce a constant damping term to control the error between the resulting approximation of the Euler-Bernoulli system and the original one. Numerical examples verify the theoretical results and demonstrate the performance for the fast numerical method.

关键词： Euler-Bernoulli beam Pade approximation Convolution quadrature Artificial boundary condition fast algorithm

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Enhancing HEVC Efficiency: A Novel Approach to Intra-Mode Estimation Through Hadamard Cost Analysis

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IEEE ACCESS 2025年 13卷 2638-2652页

作者： Tariq, Junaid Javed, Imran Sadiq, Touseef Rahman, Hameedur Farooqi, Ashfaq Hussain Ijaz, Amir Natl Univ Modern Languages Dept Comp Sci Rawalpindi Campus Islamabad 44000 Pakistan Univ Agder Ctr Artificial Intelligence Res Dept Informat & Commun Technol N-4879 Grimstad Norway Air Univ Fac Comp & Artificial Intelligence Dept Comp Games Dev Islamabad 44230 Pakistan Air Univ Fac Comp & Artificial Intelligence Dept Comp Sci Islamabad 44230 Pakistan Univ Turku Dept Comp Turku 20014 Finland

In the realm of video coding, the quest for enhanced efficiency is unending. This study introduces a novel optimization in High Efficiency Video Coding (HEVC) by refining intra-mode estimation through Hadamard cost analysis. With the rapid evolution of codecs, real-time applications demand more than ever from the complexity of intra-mode selection. Here we show how by employing a refined approach to the rate distortion optimization (RDO) module, we achieve a 5.8% reduction in HEVC complexity and a minor yet notable -0.02% improvement in Bjontegaard Delta Bit Rate (BD-BR). Our method stands out by not only reducing computational load but also by improving bit-rate, a rare feat in the literature. By integrating this approach, future versions of HEVC could witness a significant leap in performance. We believe our findings contribute to the broader context of video compression technologies, inviting further exploration and development.

关键词： Costs Complexity theory Encoding Bit rate Spirals Optimization Codecs Video compression Social networking (online) Image coding Rough mode decision rate distortion optimization intra mode fast algorithm

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fast MULTISCALE FUNCTIONAL ESTIMATION IN OPTIMAL EMG PLACEMENT FOR ROBOTIC PROSTHESIS CONTROLLERS

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JOURNAL OF INTEGRAL EQUATIONS AND APPLICATIONS 2023年第3期35卷 355-374页

作者： Ren, Jin Song, Guohui Tabacu, Lucia Xu, Yuesheng Old Dominion Univ Dept Math & Stat Norfolk VA 23529 USA

Electromyogram (EMG) signals play a significant role in decoding muscle contraction information for robotic hand prosthesis controllers. Widely applied decoders require a large amount of EMG signals sensors, resulting in complicated calculations and unsatisfactory predictions. By the biomechanical process of single degree-of-freedom human hand movements, only several EMG signals are essential for accurate predictions. Recently, a novel predictor of hand movements adopted a multistage sequential adaptive functional estimation (SAFE) method based on the historical functional linear model (FLM) to select important EMG signals and provide precise projections. However, SAFE repeatedly performs matrix-vector multiplications with a dense representation matrix of the integral operator for the FLM, which is computationally expensive. Noting that with a properly chosen basis, the representation of the integral operator concentrates on a few bands of the basis, the goal of this study is to develop a fast multiscale SAFE (MSAFE) method aiming at reducing computational costs while preserving (or even improving) the accuracy of the original SAFE method. Specifically, a multiscale piecewise polynomial basis is adopted to discretize the integral operator for the FLM, resulting in an approximately sparse representation matrix, and then the matrix is truncated to a sparse one. This approach not only accelerates computations but also improves robustness against noises. When applied to real hand movement data, MSAFE saves 85%similar to 90% computing time compared with SAFE, while producing better sensor selection and comparable accuracy. In a simulation study, MSAFE shows stronger stability in sensor selection and prediction accuracy against correlated noise than SAFE.

关键词： electromyography signal robotic prosthesis controllers functional variable selection group LASSO multiscale piecewise polynomial basis sparse matrix fast algorithm

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Improved discrete Tchebichef transform approximations for efficient image compression

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2024年第1期21卷 12-12页

作者： Mefoued, Abdelkader Kouadria, Nasreddine Harize, Saliha Doghmane, Noureddine BADJI Mokhtar Annaba Univ LASA Lab Dept Elect Annaba 23000 Algeria

In recent years, the Discrete Tchebichef Transform (DTT) has gained popularity as a signal processing tool for image and video compression due to its efficient coding and decorrelation properties. However, in the context of real-time applications and embedded systems, it is critical to develop approximate algorithms with reduced complexity and energy consumption. While three DTT approximations have been proposed to date, there is still room for further improvements. To address this gap, we propose two new low-complexity DTT approximations that employ a modified deviation metric, resulting in better compression efficiency and reduced complexity. We validate our proposed methods by implementing them on the Xilinx Virtex-6 XC6VSX475T-1FF1759-2 Field Programmable Gate Array (FPGA) through rapid prototyping. Our proposed transformations exhibit superior performance in terms of hardware resources and energy consumption, particularly for 1D 8 inputs. Furthermore, compared to the state-of-the-art DTT approximations in image compression, our proposed transformations demonstrate a quality gain of up to 2 dB. Overall, our proposed approximations provide a promising trade-off between image quality, hardware resources, and energy consumption, making them ideal for real-time applications and embedded systems.

关键词： DTT approximation fast algorithm Image compression Low complexity FPGA implementation

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Structure and Principles of Operation of a Quaternion VLSI Multiplier

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APPLIED SCIENCES-BASEL 2024年第18期14卷 8123页

作者： Cariow, Aleksandr Naumowicz, Mariusz Handkiewicz, Andrzej West Pomeranian Univ Technol Fac Comp Sci & Informat Technol PL-70310 Szczecin Poland Poznan Univ Tech Fac Comp Ul Piotrowo 3a PL-60965 Poznan Poland Jacob Paradise Univ Fac Technol PL-66400 Gorzow Wielkopolski Poland

The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository.

关键词： hypercomplex numbers quaternion multiplier fast algorithm matrix-vector multiplication hardware implementation FPGA ASIC

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