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Power-Aware Testing for Maximum fault coverage in Analog and Digital Circuits Simultaneously

IETE TECHNICAL REVIEW 2022年第6期39卷 1395-1409页

作者： Singh, Vivek Kumar Sarkar, Trupa Pradhan, Sambhu Nath Natl Inst Technol Agartala ECE Dept Agartala India

In this paper, a method for maximum fault coverage with minimum power dissipation, during the testing of analog and digital circuits of mixed-signal System-on-Chip (SOC) simultaneously using Genetic Algorithm, (GA) is proposed. Mixed-signal SOC consists mainly of an analog block, a digital block and a DAC/ADC (Digital to Analog Converter/Analog to Digital Converter). Due to the presence of analog and digital circuits in mixed-signal SOCs, the testing procedure is difficult from that of only analog or digital circuit testing. Here stuck at 0/1 faults are considered for digital circuits, and stuck open/short faults are considered for analog circuits. In analog testing fault modeling, fault injection and fault simulation are done. The outputs of the analog block and some independent digital signals are given to the digital block. The GA-based approach is used for power-aware ordering of test patterns considering pattern dependency on previous patterns at the input of digital block as input patterns. The effect of noise on analog test signals has also been investigated here with the area analysis of the circuit. An average of 92.43% fault coverage and 13.56% maximum power saving is achieved when this methodology is applied to ITC 97 (Analog block) and ISCAS 85 (Digital block) benchmark circuits, respectively. A trade-off between fault coverage and power dissipation has been presented.

关键词： ADC fault coverage Genetic Algorithm (GA) mixed-signal Operational Amplifier (Op-Amp) power dissipation SOC

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fault coverage Analysis using Sneak Path based Testing in Memristor Circuits 31

Fault Coverage Analysis using Sneak Path based Testing in Me...

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31st IEEE Microelectronics Design and Test Symposium (MDTS)

作者： Joshi, Rasika Acken, John M. Intel Corp Hillsboro OR 97124 USA Portland State Univ Portland OR 97207 USA

ISBN: (纸本)9781665468169

Testing memristor crossbar arrays is required to ensure high quality. However, inefficient testing can be prohibitively expensive. To evaluate the quality and efficiency of a test requires identifying the underlying relationship between fault coverage and test time as measured by faults detected per added test vector. This work describes a test methodology that utilizes sneak paths for efficient test generation. This work further describes the relationship between added test vectors and improved fault coverage for the efficient test generation methodology.

关键词： fault coverage test time memristors sneak paths

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Balanced Scan Chain Analysis to Improve fault coverage in VLSI circuits 6

Balanced Scan Chain Analysis to Improve Fault Coverage in VL...

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6th International Conference on Inventive Computation Technologies (ICICT)

作者： Somanathan, Geethu Remadevi Bhakthavathchalu, Ramesh Krishnakumar, M. Amrita Vishwa Vidyapeetham Dept Elect & Commun Engn Amritapuri India KSEBL Thiruvananthapuram Kerala India

ISBN: (纸本)9781728185019

Built-in-Self-Test allows a circuit to test itself, and finds more use with standalone and mission critical applications like medical or automotive. Testability of a circuit is a key factor which determines the level of testing that can be done to fmd faults in the circuit. Scan chains can be used in circuits with flip-flops to enhance the testability. Effectiveness of scan designs largely depends on the quantity of flip-flops and length, number of scan chains. This paper analyses the circuits with full scan designs using the cases of maximum number and minimum number of equal length scan chains in all circuits. The number of PI/PO, total faults, fault coverage, CPU time, test inputs required are compared. The experiments are done on IS CAS '89 benchmarked circuits.

关键词： BIST Scan chains Balanced scan chain Test time fault coverage

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fault coverage-Aware Metrics for Evaluating the Reliability Factor of Solar Tracking Systems

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ENERGIES 2021年第4期14卷 1074页

作者： Rotar, Raul Jurj, Sorin Liviu Opritoiu, Flavius Vladutiu, Mircea Politehn Univ Timisoara Comp & Informat Technol 2 V Parvan Blvd Timisoara 300223 Romania

This paper presents a mathematical approach for determining the reliability of solar tracking systems based on three fault coverage-aware metrics which use system error data from hardware, software as well as in-circuit testing (ICT) techniques, to calculate a solar test factor (STF). Using Euler's named constant, the solar reliability factor (SRF) is computed to define the robustness and availability of modern, high-performance solar tracking systems. The experimental cases which were run in the Mathcad software suite and the Python programming environment show that the fault coverage-aware metrics greatly change the test and reliability factor curve of solar tracking systems, achieving significantly reduced calculation steps and computation time.

关键词： solar tracking systems solar test factor solar reliability factor availability fault coverage

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A Methodology for Identification of Internal Nets for Improving fault coverage in Analog and Mixed Signal Circuits

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2020年第6期36卷 719-730页

作者： Sanyal, Sayandeep Bhattacharya, Mayukh Patra, Amit Dasgupta, Pallab Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur W Bengal India Synopsys Inc San Diego CA USA Indian Inst Technol Kharagpur Dept Elect Engn Kharagpur W Bengal India

Traditional literature on analog testing deals with the propagation of faults to the output ports of a circuit. Often the percentage of detected faults remains low because suitable stimuli cannot be found for propagating certain faults to the outputs. Existing technology supports monitoring internal nets of a circuit, thereby improving fault detection by observing their effect on internal nets. However, this approach is feasible only if the number of internal nets probed by the built-in test structure is limited. This paper presents a structured approach that identifies a small well-chosen subset of internal nets which, when probed, can increase the coverage of analog faults. Further, it describes a formal methodology to identify distinct sub-circuits in a given design, that could be independently probed for detection of faults. Thus, for a given fault universe, the complexity of simulations can be reduced significantly by simulating only the sub-circuits rather than the entire design. We utilize the speed of DC analysis, some common features of analog signals, and partitioning of the transistor netlist using a Channel Connected Graph to accomplish this outcome. We report significant improvement in fault coverage on several circuits including some Analog/Mixed-Signal benchmarks.

关键词： fault coverage Analog faults Analog circuits Mixed-signal circuits Channel connected graphs

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A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications 29

A comparative analysis of LFSR cascading for hardware effici...

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29th IEEE Asian Test Symposium (ATS)

作者： Alamgir, Arbab Bin A'ain, Abu Khari Paraman, Norlina Sheikh, Usman Ullah Grout, Ian Univ Teknol Malaysia Fac Engn Sch Elect Engn Johor Baharu Malaysia Univ Limerick Dept Elect & Comp Engn Limerick Ireland

ISBN: (纸本)9781728174679

Determination of the most appropriate test set is a critical task for high fault coverage in digital testing. Linear feedback shift registers (LFSR) is a common choice to generate pseudo-random patterns for any circuit under test. However, literature shows that pseudo-random generation is incapable of achieving high fault coverage in complex circuits under test. Moreover, a proportional amount of LFSR hardware is loaded with additional circuitry to implement weighted random and mixed-mode reseeding techniques. Despite dense research around weighted random and mixed-mode reseeding techniques, test pattern generation remains a high-cost block in built-in self-test architectures. This research paper uses the parallel concatenation of LFSRs to propose a simple, uniform, and scalable test pattern generator architecture for BIST applications. The proposed test pattern generator reduces the large use of memory elements in an LFSR. Moreover, the parallel concatenation of LFSRs enables the test pattern generator to supply divergent test sequences for comparatively high fault coverage. fault simulations on combinational profiles of ISCAS'89 benchmark circuits show higher fault coverage with low hardware overhead as compared to standard LFSR.

关键词： Test pattern generation Built-in self-test Parallel Cascading Linear Feedback shift register Hardware efficiency fault coverage

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Scalable fault coverage Estimation of Sequential Circuits without fault Injection

Scalable Fault Coverage Estimation of Sequential Circuits wi...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Javvaji, Pavan Kumar Tragoudas, Spyros Kondapuram, Ganesh Southern Illinois Univ Dept Elect & Comp Engn Carbondale IL 62901 USA Intel Corp Santa Clara CA 95051 USA

Industrial and automotive standards for safety critical System on Chips require fault coverage at the gate level. A scalable estimation method that avoids fault injection is presented. It is statistically correlated t... 详细信息

ISBN: (纸本)9781538648810

关键词： Functional Safety fault coverage Regression IEC 61508 ISO 26262

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fault coverage of Memory Polarized Mho Elements with Time Delays 70

Fault Coverage of Memory Polarized Mho Elements with Time De...

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70th Annual Conference on Protective Relay Engineers (CPRE)

作者： Hulme, Jason Department of Computer Science New Paltz NY

ISBN: (纸本)9781538615812

This paper analyzes the effect of time delays on the fault resistance coverage of memory polarized distance elements. A high voltage, electrically short, transmission line with a permissive overreaching transfer trip (POTT) protection scheme and mho step distance backup will be analyzed to show the reduction in fault resistance coverage caused by capacitive voltage transformer blocking logic, communications delays, and time delays associated with step distance backup. The reduction in fault coverage due to memory voltage decay will be compared to the approximate arc fault resistance encountered for faults on the transmission line. Solutions to deficiencies in the fault resistance coverage will be examined such as replacing the POTT scheme with DCB or quadrilateral distance elements to create a more dependable protection scheme.

关键词： delays power transmission faults power transmission protection fault coverage Memory Memory fault resistance Voltage transformers delay time delay Transmission Lines direct current circuit breakers Elements

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A high fault coverage test approach for communication channels in network on chip

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MICROELECTRONICS RELIABILITY 2017年 75卷 178-186页

作者： Aghaei, Babak Islamic Azad Univ Malekan Branch Dept Comp Engn Malekan Iran

This paper proposes a new high fault coverage test approach for short faults in Network on Chip communication channels. The proposed approach consists of a built in self-test as well as a Packet/flit Comparing Module (PCM) embedded in the network adapter and a router, respectively. The approach is mainly characterized by the fact that, the detection, location, and routing table updating processes are simultaneously carried out after which the test time is minimized. The approach with high scalability leads to 100% test coverage and 89.5% capability of diagnosing faulty channels in one round (two phases). The simulation results show that the approach hardware and time cost is optimized compared with the previous methodologies. (C) 2017 Elsevier Ltd. All rights reserved.

关键词： Network on Chip Communication test fault detection fault location Test coverage fault coverage

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Reliability Analysis of Flight Control System under Perfect and Imperfect fault coverage

Reliability Analysis of Flight Control System under Perfect ...

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IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology

作者： Poonam Rani G. L. Pahuja Department of Electrical Engineering National Institute of Technology

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

Systems such as aircraft control need very high levels of reliability, so redundancy is adopted for acquiring the same. The reliability of the system gets affected due to the coverage. When a component in a system fails, the detection and isolation of the system are less than perfect. This is called as coverage. fault coverage Model is of two types, Perfect fault coverage Mode (PFCM) and Imperfect fault coverage Mode (IFCM). In PFCM, coverage is perfect i.e. its value is unity while in IFCM, coverage is not perfect i.e. it can take any value other than unity. Flight Control System (FCS) also falls under this category. FCS consists of sensor, computer, actuator and two communication channel. In this paper, three different configurations of FCS are considered in terms of Redundancy Corporation. For all the three systems, reliability indices for both PFCM and IFCM have been calculated by considering communication channel as perfect and imperfect. It has been observed that IFCM reliability is less than PFCM, hence IFCM depicts true system. Then, some comparisons have been done among the reliability of three systems under perfect/imperfect fault coverage by taking communication system as perfect and imperfect. Hence, out of these three systems best one is pointed out.

关键词： Element level coverage fault level coverage Imperfect fault coverage Perfect fault coverage Reliability index System reliability fault coverage Perfect reliability index Imperfect Communication channels Reliability analysis Flight control systems fault level coverage Aircraft control redundancy

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