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International Conference on Modern Problems of Radio Engineering, Telecommunication and Computer Science

作者： Elvira, Kulak Maryna, Karninska Olesia, Guz Alexander, Parfentiy Kharkov Natl Univ Radio Elect Design Auromat Dept UA-61166 Kharkov Ukraine

it is proposed strategy of bottlenecks choice in digital device and procedure of modification for test quality improving based on methods of testability analysis and IEEE Computer Society standards.

ISBN: (纸本)9781424413218

it is proposed strategy of bottlenecks choice in digital device and procedure of modification for test quality improving based on methods of testability analysis and IEEE Computer Society standards.

关键词： IEEE computer society standards controllability observability testability deterministic ATPG fault coverage asynchronous circuits

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fault coverage Analysis using Sneak Path based Testing in Memristor Circuits 31

Fault Coverage Analysis using Sneak Path based Testing in Me...

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31st IEEE Microelectronics Design and Test Symposium (MDTS)

作者： Joshi, Rasika Acken, John M. Intel Corp Hillsboro OR 97124 USA Portland State Univ Portland OR 97207 USA

ISBN: (纸本)9781665468169

Testing memristor crossbar arrays is required to ensure high quality. However, inefficient testing can be prohibitively expensive. To evaluate the quality and efficiency of a test requires identifying the underlying relationship between fault coverage and test time as measured by faults detected per added test vector. This work describes a test methodology that utilizes sneak paths for efficient test generation. This work further describes the relationship between added test vectors and improved fault coverage for the efficient test generation methodology.

关键词： fault coverage test time memristors sneak paths

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A BIST pattern generator design for near-perfect fault coverage

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IEEE TRANSACTIONS ON COMPUTERS 2003年第12期52卷 1543-1558页

作者： Chatterjee, M Pradhan, DK Integrated Device Technol Inc Internetworking Prod Div Santa Clara CA 95054 USA Univ Bristol Dept Comp Sci Bristol BS8 1UB Avon England

A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The design methodology is circuit-specific and uses synthesis techniques to design BIST generators. The pattern generator consists of two components: a pseudorandom pattern generator (like an LFSR or, preferably, a GLFSR) and a combinational logic to map the outputs of the pseudorandom pattern generator. This combinational logic is synthesized to produce a given set of target patterns by mapping the outputs of the pseudorandom pattern generator. It is shown that, for a particular CUT, an area-efficient combinational logic block can be designed/synthesized to achieve 100 (or almost 100) percent single stuck-at fault coverage using a small number of test patterns. This method is significantly different from weighted pattern generation and can guarantee testing of all hard-to-detect faults without expensive test point insertion. Experimental results on common benchmark netlists demonstrate that the fault coverage of the proposed pattern generator is significantly higher compared to conventional pattern generation techniques. The design technique for the logic mapper is unique and can be used effectively to improve existing pattern generators for combinational logic and scan-based BIST structures.

关键词： linear feedback shift registers built-in self-test scan synthesis test pattern generation fault coverage core logic SOC

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A Generalized fault coverage Model for Linear Time-Invariant Systems

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IEEE TRANSACTIONS ON RELIABILITY 2009年第3期58卷 553-567页

作者： Dominguez-Garcia, Alejandro D. Kassakian, John G. Schindall, Joel E. Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA MIT Electromagnet & Elect Syst Lab Cambridge MA 02139 USA

This paper proposes a fault coverage model for Linear Time-Invariant (LTI) systems subject to uncertain input. A state-space representation, defined by the state-transition matrix, and the input matrix, is used to represent LTI system dynamic behavior. The uncertain input is considered to be unknown but bounded, where the bound is defined by an ellipsoid. The state-transition matrix, and the input matrix must be such that, for any possible input, the system dynamics meets its intended function, which can be defined by some performance requirements. These performance requirements constrain the system trajectories to some region of the state-space defined by a symmetrical polytope. When a fault occurs, the state-transition matrix, and the input matrix might be altered;and then, it is guaranteed the system survives the fault if all possible post-fault trajectories are fully contained in the region of the state-space defined by the performance requirements. This notion of guaranteed survivability is the basis to model ( in the context of LTI systems) the concept of fault coverage, which is a probabilistic measure of the ability of the system to keep delivering its intended function after a fault. Analytical techniques to obtain estimates of the proposed fault coverage model are presented. To illustrate the application of the proposed model, two examples are discussed.

关键词： Convex optimization fault coverage invariant sets linear time-invariant systems Markov reliability modeling

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fault coverage of Memory Polarized Mho Elements with Time Delays 70

Fault Coverage of Memory Polarized Mho Elements with Time De...

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70th Annual Conference on Protective Relay Engineers (CPRE)

作者： Hulme, Jason Department of Computer Science New Paltz NY

ISBN: (纸本)9781538615812

This paper analyzes the effect of time delays on the fault resistance coverage of memory polarized distance elements. A high voltage, electrically short, transmission line with a permissive overreaching transfer trip (POTT) protection scheme and mho step distance backup will be analyzed to show the reduction in fault resistance coverage caused by capacitive voltage transformer blocking logic, communications delays, and time delays associated with step distance backup. The reduction in fault coverage due to memory voltage decay will be compared to the approximate arc fault resistance encountered for faults on the transmission line. Solutions to deficiencies in the fault resistance coverage will be examined such as replacing the POTT scheme with DCB or quadrilateral distance elements to create a more dependable protection scheme.

关键词： delays power transmission faults power transmission protection fault coverage Memory Memory fault resistance Voltage transformers delay time delay Transmission Lines direct current circuit breakers Elements

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Test vector chains for increasing the fault coverage and numbers of detections

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IET COMPUTERS AND DIGITAL TECHNIQUES 2009年第2期3卷 222-233页

作者： Pomeranz, I. Reddy, S. M. Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA Univ Iowa Dept Elect & Comp Engn Iowa City IA 52242 USA

The authors introduce the concept of test vector chains which allows one to obtain new test vectors from existing ones through single-bit changes. A test vector chain is defined based on a pair of test vectors t(1) and t(2). It consists of a sequence of single-bit changes, which gradually modifies t1 into t2. The authors demonstrate that, based on a test set T that does not detect all the detectable target faults, it is possible to de. ne a significant number of test vector chains, which are effective in detecting yet-undetected target faults. It is also possible to find test vector chains that are effective in increasing the numbers of detections of target faults that are detected by T. Increasing the number of detections increases the coverage of untargeted faults, that is, faults that were not targeted during the generation of T. The authors study criteria for identifying the most effective test vector chains of a test set in order to avoid considering m(m 21) test vector chains for a test set of size m, and describe test generation procedures based on test vector chains.

关键词： fault coverage TEST SETS Targets Chains faults test vectors

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A high fault coverage test approach for communication channels in network on chip

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MICROELECTRONICS RELIABILITY 2017年 75卷 178-186页

作者： Aghaei, Babak Islamic Azad Univ Malekan Branch Dept Comp Engn Malekan Iran

This paper proposes a new high fault coverage test approach for short faults in Network on Chip communication channels. The proposed approach consists of a built in self-test as well as a Packet/flit Comparing Module (PCM) embedded in the network adapter and a router, respectively. The approach is mainly characterized by the fact that, the detection, location, and routing table updating processes are simultaneously carried out after which the test time is minimized. The approach with high scalability leads to 100% test coverage and 89.5% capability of diagnosing faulty channels in one round (two phases). The simulation results show that the approach hardware and time cost is optimized compared with the previous methodologies. (C) 2017 Elsevier Ltd. All rights reserved.

关键词： Network on Chip Communication test fault detection fault location Test coverage fault coverage

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fault coverage and Resource Analysis for Diverse Structures of Clock TSV fault-Tolerant Units in 3D ICs

Fault Coverage and Resource Analysis for Diverse Structures ...

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International SoC Design Conference (ISOCC)

作者： Park, Heechun Kim, Taewhan Seoul Natl Univ Sch Elect & Comp Engn Seoul South Korea

ISBN: (纸本)9781479911424

In TSV (Through-Silicon-Via) based 3D ICs, synthesizing 3D clock tree is one of the most challenging tasks. Since the clock signal is delivered to clock sinks (e.g., latches, FFs) through TSVs, any fault on a TSV in the clock tree causes a chip failure. Therefore, ensuring the reliability of clock TSVs is highly important. Instead of the naive solution using double-TSV technique, which demands significant area overhead because of the large size of TSV, a structure called TSV fault-tolerant unit is proposed to provide TSV fault tolerance with minimum area overhead. In this work, we analyze a set of diverse structures of clock TSV fault-tolerant units which include not only the existing ones but also possible variants we devised, with respect to the TSV fault coverage and resource overhead such as additional TSVs, gates, and wires required. Our analysis results can be used usefully to provide designers with a guideline on the selection of TSV fault-tolerant unit that is best suited for their 3D IC design objectives and constraints.

关键词： Circuit faults Clocks fault tolerance fault tolerant systems Logic gates Three-dimensional displays Through-silicon vias Through-silicon vias Timing devices fault tolerance Taura syndrome virus of marine penaeid shrimp three-dimensional displays fault tolerant systems Circuit faults Logic gates fault coverage clock signal

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Analysis and measurement of fault coverage in a combined ATE and BIST environment

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2004年第2期53卷 300-307页

作者： Hashempour, H Meyer, FJ Lombardi, F Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

This paper analyzes an environment which utilizes built-in self-test (BIST) and automatic test equipment (ATE), and presents closed-form expressions for fault coverage as a function of the number of BIST and ATE test vectors. This requires Incorporating the time to switch from BIST to ATE (referred to as switchover time), and utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment, we model fault coverage as a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed;this approach is initially based on fault simulation using a small set of random vectors;an estimate of the so-called detection profile of the circuit under test is established as the basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE as related testing processes.

关键词： automatic test equipment (ATE) built-in self-test (BIST) fault coverage hybrid BIST

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Efficient approaches to low-cost high-fault coverage VLSI BIST designs

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 1998年第1期34卷 63-70页

作者： Chen, CIH Wright State Univ Dept Elect Engn Dayton OH 45435 USA

This work introduces a built-in self-test (BIST) design methodology that can sequentially test large very large scale integrated (VLSI) circuits with very high fault coverage. The proposed techniques, circular BIST (CBIST) and CBIST with pseudopartial scan (PPSCAN), are modeled after the principles of the circular self-test path (CSTP). The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It is shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared with existing sequential test methods. The effectiveness of the technique has been demonstrated by applying it to practical VLSI circuits, which include: 1) the system control coprocessor (CP0) of MIPS 3000 central processing unit (CPU) core and 2) the SIMD graphic engine, namely, enhanced memory chip (EMC). The BIST results show that CBIST and its derivative CBIST with pseudopartial scan (PPSCAN) are feasible for practical VLSI designs and generate BIST with high fault coverage and low overhead.

关键词： Built-in self test fault coverage Very large scale integration

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