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A Novel Test Application Scheme for High Transition fault coverage and Low Test Cost

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2010年第6期29卷 966-976页

作者： Chen, Zhen Xiang, Dong Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China Tsinghua Univ Sch Software Beijing 100084 Peoples R China

This paper presents a new method for improving transition fault coverage in hybrid scan testing. It is based on a novel test application scheme, in order to break the functional dependence of broadside testing. The new technique analyzes the automatic test pattern generation conflicts in broadside test generation and skewed-load test generation, and tries to control the flip-flops with the most influence on fault coverage. The conflict-driven selection method selects some flip-flops that work in the enhanced scan mode or skewed-load scan mode. And the conflict-driven reordering method distributes the selected flip-flops into different chains. In the multiple scan chain architecture, to avoid too many scan-in pins, some chains are driven by the same scan-in pin to construct a tree-based architecture. Based on the architecture, the new test application scheme allows some flip-flops to work in enhanced scan or skewed-load mode, while most of others to work in the traditional broadside scan mode. With the efficient conflict-driven selection and reordering schemes, fault coverage is improved greatly, which can also reduce test application time and test data volume. Experimental results show that fault coverage based on the proposed method is comparable that of enhanced scan.

关键词： Broadside testing fault coverage hybrid scan testing test cost

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A STUDY OF fault coverage OF STANDARD AND WINDOWED WATCHDOG TIMERS

A STUDY OF FAULT COVERAGE OF STANDARD AND WINDOWED WATCHDOG ...

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IEEE International Conference on Signal Processing and Communications

作者： El-Attar, Ashraf M. Fahmy, Gamal German Univ Cairo Egypt

ISBN: (纸本)9781424412358

Both standard and windowed watchdog timers were designed to detect flow faults and ensure the safe operation of the systems they supervise. This paper studies the effect of transient failures on microprocessors, and utilizes two methods to compare the fault coverage of both watchdog timers. The first method is injecting a fault while a processor is reading an image from RAM and sending it to the VGA RAM for display. This method is implemented on FPGA, and visually demonstrates the existence of fast watchdog resets which can not be detected by standard watchdog timers, and faulty resets which occur undetected within the safe window of the windowed watchdog timers. The second method is a simulation where the fault coverage for each watchdog timer system is calculated. This simulation tries to take into consideration many factors which could affect the outcome of this comparison.

关键词： Microprocessors Watchdog timer fault coverage Flow faults

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Analysis of fault coverage and simulation of test data compactors for on-line testing control units

Analysis of fault coverage and simulation of test data compa...

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Conference on Design, Modeling, and Simulation in Microelectronics

作者： Demidenko, SN Massey Univ Inst Informat Sci & Technol Palmerston North New Zealand

ISBN: (纸本)0819439002

The paper is related to synthesis of concurrently self-testing control units providing pre-defined level of fault coverage. Compaction (compression) of test data is one of the core elements of on-line monitoring over control flow execution in terms of its integrity and correctness. Traditionally, the most widely employed compression algorithm is so-called Signature Compression. It is based on the well-established theory on cyclic coding. Cyclic coding and related error correction are very efficient tools when errors lead to inversion of some bits in the initial bit sequence. However, error types and corresponding fault models in case of control unit monitoring are different. Two new fault models for control unit test data are introduced in the paper - shortening and lengthening of the bit sequence being compressed. Results of simulation and comparison of several compression algorithms for these fault models are presented in the paper. The control units of micro-programmed type are considered through out the paper though the results can be applicable to other control unit architectures.

关键词： synthesis on-line self-checking control units fault coverage test data compression

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A Novel Test Pattern Generator with High fault coverage for BIST Design

A Novel Test Pattern Generator with High Fault Coverage for ...

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2nd International Conference on Information and Computing Science

作者： Zheng Wen-rong Wang Shu-zong Naval Univ Engn Dept Weaponry Eng Wuhan Peoples R China

ISBN: (纸本)9780769536347

A new and effective pseudorandom test pattern generator, termed GLFSR, is introduced. The test pattern generation by GLFSR achieves a higher degree of randomness. Experimental results on common benchmark CUT demonstrate that the fault coverage of the propose pattern generator is significantly higher compared to conventional pattern generation techniques. For Cut's stuck-at fault and transition faults, test pattern generator using GLFSR can attain equivalent fault coverage but fewer patterns than LFSR pattern generator. GLFSR can be used as test pattern for the architecture of BIST.

关键词： Built-in self-test Linear feedback shift registers test pattern generation fault coverage

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Balanced Scan Chain Analysis to Improve fault coverage in VLSI circuits 6

Balanced Scan Chain Analysis to Improve Fault Coverage in VL...

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6th International Conference on Inventive Computation Technologies (ICICT)

作者： Somanathan, Geethu Remadevi Bhakthavathchalu, Ramesh Krishnakumar, M. Amrita Vishwa Vidyapeetham Dept Elect & Commun Engn Amritapuri India KSEBL Thiruvananthapuram Kerala India

ISBN: (纸本)9781728185019

Built-in-Self-Test allows a circuit to test itself, and finds more use with standalone and mission critical applications like medical or automotive. Testability of a circuit is a key factor which determines the level of testing that can be done to fmd faults in the circuit. Scan chains can be used in circuits with flip-flops to enhance the testability. Effectiveness of scan designs largely depends on the quantity of flip-flops and length, number of scan chains. This paper analyses the circuits with full scan designs using the cases of maximum number and minimum number of equal length scan chains in all circuits. The number of PI/PO, total faults, fault coverage, CPU time, test inputs required are compared. The experiments are done on IS CAS '89 benchmarked circuits.

关键词： BIST Scan chains Balanced scan chain Test time fault coverage

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TPI for improving PR fault coverage of Boolean and three-state circuits 8

TPI for improving PR fault coverage of Boolean and three-sta...

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8th IEEE European Test Workshop

作者： Geuzebroek, MJ van de Goor, AJ Delft Univ Technol Dept Elect Engn Fac Informat Technol & Syst Testing Lab NL-2628 CD Delft Netherlands

ISBN: (纸本)0769519083

TPI can be used to improve the pseudo-random testability of circuit. However, many TPI algorithms are based on COP, which can only cope with Boolean circuits, while in the industry also three-state circuits are found. In this paper the testability analysis method COP and the COP based HCRF TPI algorithm are extended with three-state capabilities, and the HCRF TPI algorithm is adjusted in such a way that better PR fault coverage improvements can be achieved as well as for Boolean as for three-state circuits.

关键词： test point insertion BIST fault coverage pseudo-random COP

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Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?

Functional fault coverage: the chamber of secrets or an accu...

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9th IEEE European Test Symposium (ETS 2004)

作者： Fummi, F Marconcini, C Pravadelli, G Univ Verona Dipartimento Informat I-37100 Verona Italy

ISBN: (纸本)0769521193

More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.

关键词： functional verification ATPG fault model fault coverage

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A Rotation-Based BIST with Self-Feedback Logic to Achieve Complete fault coverage

A Rotation-Based BIST with Self-Feedback Logic to Achieve Co...

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International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

作者： Lien, Wei-Cheng Hsieh, Tong-Yu Tsai, Cheng-Tsung Lee, Kuen-Jong Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan

ISBN: (纸本)9781424484997

This paper presents a deterministic BIST technique that can efficiently achieve complete fault coverage without using any storage devices. A novel test structure containing a self-feedback logic unit and a circular shift register is proposed by which all the required deterministic patterns can be generated on-chip in real time. Experiments on ISCAS 85 benchmark circuits show that compared with previous work addressing the same problem our technique requires much less test time to achieve 100% fault coverage for all testable stuck-at faults.

关键词： Built-in self-test Circuit faults Control systems Flyback transformers ISCAS 85 benchmark circuits Shift registers System-on-a-chip Very large scale integration built-in self test circular shift register deterministic BIST technique deterministic patterns fault coverage fault diagnosis logic testing microprocessor chips on-chip real time real-time systems rotation-based BIST self-feedback logic unit shift registers testable stuck-at faults

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A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications 29

A comparative analysis of LFSR cascading for hardware effici...

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29th IEEE Asian Test Symposium (ATS)

作者： Alamgir, Arbab Bin A'ain, Abu Khari Paraman, Norlina Sheikh, Usman Ullah Grout, Ian Univ Teknol Malaysia Fac Engn Sch Elect Engn Johor Baharu Malaysia Univ Limerick Dept Elect & Comp Engn Limerick Ireland

ISBN: (纸本)9781728174679

Determination of the most appropriate test set is a critical task for high fault coverage in digital testing. Linear feedback shift registers (LFSR) is a common choice to generate pseudo-random patterns for any circuit under test. However, literature shows that pseudo-random generation is incapable of achieving high fault coverage in complex circuits under test. Moreover, a proportional amount of LFSR hardware is loaded with additional circuitry to implement weighted random and mixed-mode reseeding techniques. Despite dense research around weighted random and mixed-mode reseeding techniques, test pattern generation remains a high-cost block in built-in self-test architectures. This research paper uses the parallel concatenation of LFSRs to propose a simple, uniform, and scalable test pattern generator architecture for BIST applications. The proposed test pattern generator reduces the large use of memory elements in an LFSR. Moreover, the parallel concatenation of LFSRs enables the test pattern generator to supply divergent test sequences for comparatively high fault coverage. fault simulations on combinational profiles of ISCAS'89 benchmark circuits show higher fault coverage with low hardware overhead as compared to standard LFSR.

关键词： Test pattern generation Built-in self-test Parallel Cascading Linear Feedback shift register Hardware efficiency fault coverage

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I_DDQ testing as a component of a test suite: The need for several fault coverage metrics

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Journal of Electronic Testing 1992年第4期3卷 305-316页

作者： Maxwell, Peter C. Aitken, Robert C. Design Technology Center Hewlett-Packard Company Santa Clara 95052 CA United States

This article is concerned with the role of IDDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is bet... 详细信息

This article is concerned with the role of I_DDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults. To demonstrate the need for increasingly stringent fault coverage requirements, an analysis is given of the relationship between quality, fault coverage and chip area. This analysis shows that as chip area increases, fault coverage must also increase to maintain constant quality levels. Data are then presented from a production part tested with I_DDQ, scan, timing and functional tests. To realistically fault grade I_DDQ tests, three different coverage metrics are considered. The data show differences in tester failures compared to these coverage metrics, depending on whether one uses total I_DDQ failures (parts which fail I_DDQ regardless of whether they fail other tests as well) or unique I_DDQ failures (parts which fail only I_DDQ). The relative effectiveness of the different components of the full test suite are analyzed and it is demonstrated that no component can be removed without suffering a reduction in quality. © 1992 Kluwer Academic Publishers.

关键词： Current testing fault coverage functional testing physical defects quality scan

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