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Definition and generation of partially-functional broadside tests

IET COMPUTERS AND DIGITAL TECHNIQUES 2009年第1期3卷 1-13页

作者： Pomeranz, I. Reddy, S. M. Purdue Univ Sch ECE W Lafayette IN 47907 USA Univ Iowa ECE Dept Iowa City IA 52242 USA

Functional and pseudo-functional broadside tests were defined to address the fact that testing a circuit under non-functional operation conditions, which are made possible by scanning in unreachable states, may result in overtesting or unnecessary yield loss. One of the reasons cited for overtesting is the high switching activity possible with unreachable states. Functional broadside tests allow only reachable states as scan-in states in order to address this issue. However, the exclusive use of functional (or pseudo-functional) broadside tests may result in a loss of fault coverage, which may be a concern for the long-term reliability of the chip. To address this issue, a new class of tests is defined, which is referred to as partially-functional broadside tests. The definition of a partially-functional broadside test allows the scan-in state to be an unreachable state. It measures the amount of deviation from functional operation by considering the minimum Hamming distance between the scan-in state and a reachable state. With a smaller minimum Hamming distance, the number of state variables that operate under functional operation conditions is likely to be higher. A procedure for computing what are called partially-reachable states, which are used for generating partially-functional broadside tests is described. We demonstrate that the switching activity under partially-functional broadside tests is close to that of functional broadside tests. Thus, partially-functional broadside tests operate the circuit under conditions that are close to functional operation conditions, helping to avoid overtesting because of high switching activity while improving fault coverage.

关键词： circuit testing fault diagnosis fault coverage circuit reliability partially-functional broadside tests scan-in state minimum Hamming distance long-term reliability

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Efficient static compaction techniques for sequential circuits based on reverse-order restoration and test relaxation

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2006年第11期25卷 2556-2564页

作者： El-Maleh, Aiman H. Khursheed, S. Saqib Sait, Sadiq M. King Fahd Univ Petr & Minerals Dept Comp Engn Dhahran 31261 Saudi Arabia

The authors present efficient reverse-order-restoration (ROR)-based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation-based restoration of test subsequences, the authors' technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using a state traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation., Experimental results demonstrate the effectiveness of the proposed techniques.

关键词： fault coverage linear reverse-order restoration (LROR) state traversal (ST) static compaction test relaxation

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ON THE DESIGN OF A HIGHLY TESTABLE CELL LIBRARY

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1992年第1-5期35卷 383-390页

作者： SARAIVA, M SANTOS, MB CASIMIRO, AP TEIXEIRA, IM TEIXEIRA, JP INESC ISTCEAUTLP-1017 LISBONPORTUGAL

In this paper, a new methodology for physical testability analysis is used to derive a new cell library, which can ensure a high coverage of realistic faults, using test patterns derived for Line Stuck-at (LSA) fault detection. The increased testability obtained with this new library, with constrained area overhead is demonstrated, by means of a test chip implementing one of ISCAS'85 benchmarks (c432) and test circuitry to allow Boundary Scan Test (BST), Built-In Self Test (BIST) and Scan Test of the c432. Simulation results show that, for a 2-metal, CMOS process line dominated by bridging defects, the realistic fault coverage, FC(g) can be higher than the gate-level, LSA fault coverage, FC. Interactive cell design is also shown to be rewarding, since increased testability can be obtained. This result is important, since IC design is highly repetitive;hence, a limited effort in cell layout improvement can introduce a significant design improvement.

关键词： BIST Built-in self test BRI bridging fault BST Boundary scan test DFT design for testability DL defect level FC fault coverage LE logic element LOP line open fault LSA line stuck-at PhFM physical failure mode PU/PD pull-up/pull-down TSON transistor stuck-on TSOP transistor stuck-open

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On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams

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MICROELECTRONICS JOURNAL 2017年 67卷 88-100页

作者： Biswal, Pradeep Kumar Biswas, Santosh IIT Guwahati Dept Comp Sci & Engn Gauhati India

Nowadays On-Line Testing (OLT) has became one the essential technique to detect faults in digital VLSI circuits which occur during their normal operation. However, most of the works on OLT reported in the literature are at the gate level and these techniques take reasonable computational time. The major reason being these schemes work at bit level, leading to state explosion problem. This issue can be addressed by developing OLT schemes at higher description levels of the circuits. In this paper, we present an OLT scheme at Register Transfer Level (RTL) description using High Level Decision Diagrams (HLDDs) and design corresponding on-line tester circuits. Experiments on different HLSynth92 benchmark circuits show that the test generation time is greatly improved using HLDDs, thus, large circuits can be easily handled. Further, it achieves lower area overhead at similar fault coverage compared to OLT schemes at gate level.

关键词： RTL description On-Line Testing High Level Decision Diagram Test set generation fault coverage Area overhead fault detection latency

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Optimal zero-aliasing space compaction of test responses

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IEEE TRANSACTIONS ON COMPUTERS 1998年第11期47卷 1171-1187页

作者： Chakrabarty, K Murray, BT Hayes, JP Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA GM Corp Ctr Res & Dev Warren MI 48090 USA Univ Michigan Dept Elect Engn & Comp Sci Adv Comp Architecture Lab Ann Arbor MI 48109 USA

Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q 1.

Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q << k, a process termed space compaction. The effectiveness of such a compaction method can be measured by its compaction ratio c = k/q. A high compaction ratio can introduce aliasing, which occurs when a faulty test response maps to the fault-free signature. We investigate the problem of designing zero-aliasing space compaction circuits with maximum compaction ratio c(max). We introduce a graph representation of test responses to study the space compaction process and relate space compactor design to a graph coloring problem. Given a circuit under test, a fault model, and a test set, we determine q(min), which yields c(max) = k/q(min). This provides a fundamental bound on the cost of signature-based BIST. We show that q(min) less than or equal to 2 for all the ISCAS 85 benchmark circuits. We develop a systematic design procedure for the synthesis of space compaction circuits and apply it to a number of ISCAS 85 circuits. Finally, we describe multistep compaction, which allows zero aliasing to be achieved with any q, even when q(min) > 1.

关键词： aliasing built-in self-testing fault coverage graph coloring multistep compaction

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A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging faults in Integrated Circuits

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2023年第3期39卷 323-346页

作者： Biswal, Pradeep Kumar IIIT Bhagalpur Dept CSE Bhagalpur India

This paper presents a novel flexible concurrent testing scheme for non-feedback and feedback bridging faults in integrated circuits. All the existing concurrent testing schemes for non-feedback and feedback bridging faults available in the literature are designed with very straightforward manner and these schemes do not provide any idea regarding flexibility in design of the tester circuit. However, providing flexibility in design of the tester circuit is one of the important criteria to be included in concurrent testing of modern integrated circuits. To the best of my knowledge, the proposed scheme will be treated as first concurrent testing scheme that provides flexibility in design of the tester circuit for both non-feedback and feedback bridging faults. This work aims to provide flexibility in tester circuit design by dropping some of wires that are tapped from Circuit Under Test (CUT) to the tester circuit. Dropping some of tap wires from CUT to the tester circuit reduces load on CUT and this helps in reducing the area overhead of the tester circuit. Thus, flexibility in concurrent testing is achieved by dropping some of tap wires during design of tester circuit. Further, dropping some of tap wires (flexibility) in tester circuit design provides a trades-off analysis between area overhead, fault coverage and fault detection latency. The proposed scheme is verified using different ISCAS89 benchmark circuits and results illustrate that flexibility in design of tester circuit is achieved through dropping some of tap wires from CUT to the tester circuit. Further, it reduces area overhead greatly with minimal compromise in fault coverage.

关键词： Concurrent testing Bridging fault model Reduced ordered binary decision diagram Area overhead fault coverage fault detection latency

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A built-in self-test and diagnosis strategy for chemically assembled electronic nanotechnology

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2007年第2-3期23卷 131-144页

作者： Brown, Jason G. Blanton, R. D. Carnegie Mellon Univ Dept Elect & Comp Engn Ctr Silicon Syst Implementat Pittsburgh PA 15213 USA

Chemically assembled electronic nanotechnology (CAEN) is under intense investigation as a possible alternative or complement to CMOS-based computing. CAEN is a form of molecular electronics that uses directed self-assembly and self-alignment to construct electronic circuits from nanometer-scale devices that exploit quantum-mechanical effects. Although expected to have densities greater than 10(8) gate-equivalents/cm(2), CAEN-based systems may possibly exhibit defect densities of up to 10%. The highly defective CAEN circuits will therefore require a completely new approach to manufacturing computational devices. In order to achieve any level of significant yield, it will no longer be possible to discard a device once a defect is found. Instead, a method of using defective chips must be devised. A testing strategy is developed for chemically assembled electronic nanotechnology (CAEN) that takes advantage of reconfigurability to achieve 100% fault coverage and nearly 100% diagnostic accuracy. This strategy is particularly suited for regular architectures with high defect densities.

关键词： fault diagnosis integrated circuit testing logic testing nanoelectronics fault coverage fault diagnostic accuracy high defect densities nanofabrication reconfigurability regular architectures nanoFabric

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An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2011年第4期27卷 477-484页

作者： Sun, Haijun Zeng, Yongjia Li, Pu Lei, Shaochong Shao, Zhibiao Zhengzhou Univ Sch Informat Engn Zhengzhou 450001 Peoples R China Xi An Jiao Tong Univ Dept Microelect Xian 710049 Peoples R China

This paper presents a novel seed-based test pattern generator (SB-TPG). The core of SB-TPG is a seed sequence generator. A coverage-driven seed generation algorithm has been proposed to generate the optimized seeds. The test sequence generated by SB-TPG is a single input change (SIC) sequence that can significantly reduce test power for test-per-clock built-in self-test (BIST). Further, seed-masking technique has been put forward to filter those power-consuming seeds, thus reducing test power for test-per-scan BIST. Experimental results show that SB-TPG can achieve high fault coverage with short test length, low power and small hardware overhead.

关键词： Test pattern generator (TPG) Seed Single input change (SIC) sequence Built-in self-test (BIST) fault coverage Low power

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On Testing Hierarchies for Protocols

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IEEE-ACM TRANSACTIONS ON NETWORKING 1993年第5期1卷 590-599页

作者： Sidhu, Deepinder P. Motteler, Howard Vallurupalli, Raghu Univ Maryland Baltimore Cty Dept Comp Sci Maryland Ctr Telecommun Res Baltimore MD 21228 USA Univ Maryland Inst Adv Comp Studies College Pk MD 20742 USA

Consider a protocol specification represented as a fully specified Mealy automata, and the problem of testing an implementation for conformance to such a specification. No single sequence-based test can be completely reliable, if we allow for the possibility of an implementation with an unknown number of extra states. We define a hierarchy of test sequences, parameterized by length of behaviors under test. For the reset method of conformance testing, we prove that the hierarchy has the property that any fault detected by test i is also detected by test i + 1, and show that this sequence of tests converges to a reliable conformance test. For certain bridge sequence methods for constructing test sequences, this result does not always hold. In experiments with several specifications, we observe that given a small number of extra states in an implementation, our sequence of tests converge to total fault coverage for small values of i, for both reset and bridge sequence methods. We also observe that choice of characterizing sequence has less effect on fault coverage than choice of behavior length or number of extra states in the implementation.

关键词： Protocols conformance testing testing hierarchies optimal length test sequences faults fault coverage

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A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

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MICROELECTRONICS JOURNAL 2015年第7期46卷 598-616页

作者： Biswal, Pradeep Kumar Biswas, Santosh Indian Inst Technol Dept Comp Sci & Engn Gauhati 781039 India

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults. (C) 2015 Elsevier Ltd. All rights reserved.

关键词： On-line testing Bridging fault model Ordered Binary Decision Diagrams fault coverage Area overhead

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