The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zero-aliasing (aliasing-free) space compression hard...
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ISBN:
(纸本)9781467346214
The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zero-aliasing (aliasing-free) space compression hardware for single stuck-line faults, extending well-known concept of conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test (CUT), the method introduces the notion of faultdetectioncompatibility and conditionalfaultdetectioncompatibility (conditional upon some other pair of response data outputs being simultaneously faultdetection compatible) with respect to two-input AND/NAND and/or OR/NOR logic. The process is illustrated with the design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA, FSIM and COMPACTEST, though, because of space constraints, only some partial results on simulation on ISCAS 89 full-scan sequential benchmark circuits using ATALANTA are provided here.
The design of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent yea...
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The design of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper discusses approach to realizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of faultdetectioncompatibility and conditionalfaultdetectioncompatibility (conditional upon some other response output pair being simultaneously faultdetection compatible) with respect to two-input AND/NAND, OR/NOR and XOR/XNOR logic, respectively. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.
The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zero-aliasing (aliasing-free) space compression hard...
详细信息
ISBN:
(纸本)9781467346214
The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zero-aliasing (aliasing-free) space compression hardware for single stuck-line faults, extending well-known concept of conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test (CUT), the method introduces the notion of faultdetectioncompatibility and conditionalfaultdetectioncompatibility (conditional upon some other pair of response data outputs being simultaneously faultdetection compatible) with respect to two-input AND/NAND and/or OR/NOR logic. The process is illustrated with the design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA, FSIM and COMPACTEST, though, because of space constraints, only some partial results on simulation on ISCAS 89 full-scan sequential benchmark circuits using ATALANTA are provided here.
Synthesizing aliasing-free space compactor for built-in self-testing of very large scale integration circuits and systems is of great importance, especially because of the design paradigm shift in recent years from sy...
详细信息
ISBN:
(纸本)9781457717710
Synthesizing aliasing-free space compactor for built-in self-testing of very large scale integration circuits and systems is of great importance, especially because of the design paradigm shift in recent years from system-on-board to system-on-chip. This paper investigates and provides additional results on a recently developed approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of faultdetectioncompatibility and conditionalfaultdetectioncompatibility (conditional upon some other response output pair being simultaneously faultdetection compatible) with respect to two-input XOR/XNOR logic. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems (ISCAS 85) combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the importance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.
Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years...
详细信息
Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults. For a pair of response outputs of the circuit under test, the method uses the notion of faultdetectioncompatibility and conditionalfaultdetectioncompatibility (conditional upon some other response output pair being simultaneously faultdetection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits (results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.
Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years...
详细信息
ISBN:
(纸本)9781424479351
Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, utilizing well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method uses the notion of faultdetectioncompatibility and conditionalfaultdetectioncompatibility ( conditional upon some other response output pair being simultaneously faultdetection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits ( results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.
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