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IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

作者： Das, Sunil R. Shaw, Danny L. Biswas, Satyendra N. Assaf, Mansour H. Morton, Scott Ozkarahan, Irem Petriu, Emil M. Groza, Voicu Troy Univ Coll Arts & Sci Dept Comp Sci Montgomery AL 36103 USA

ISBN: (纸本)9781467346214

The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zero-aliasing (aliasing-free) space compression hardware for single stuck-line faults, extending well-known concept of conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test (CUT), the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other pair of response data outputs being simultaneously fault detection compatible) with respect to two-input AND/NAND and/or OR/NOR logic. The process is illustrated with the design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA, FSIM and COMPACTEST, though, because of space constraints, only some partial results on simulation on ISCAS 89 full-scan sequential benchmark circuits using ATALANTA are provided here.

关键词： Aliasing-free (zero-aliasing) space compaction ATALANTA built-in self-testing in very large scale integration circuits and systems fault detection and conditional fault detection compatibility

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Response compression in space with cascade of two-input linear and nonlinear logic

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WORLD JOURNAL OF ENGINEERING 2013年第3期10卷 283-295页

作者： Das, Sunil R. Applegate, Alexander R. Biswas, Satyendra N. Petriu, Emil M. Univ Ottawa Sch Informat Technol & Engn Fac Engn Ottawa ON K1N 6N5 Canada Troy Univ Coll Arts & Sci Dept Comp & Informat Sci Montgomery AL 36103 USA Independent Univ Sch Engn & Comp Sci Dhaka 1329 Bangladesh

The design of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper discusses approach to realizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND, OR/NOR and XOR/XNOR logic, respectively. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.

关键词： Aliasing-free space compaction ATALANTA Built-in self-testing in very large scale integration fault detection and conditional fault detection compatibility FSIM

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Data Compression Using Mixed Cascade of Nonlinear Logic

Data Compression Using Mixed Cascade of Nonlinear Logic

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IEEE International Instrumentation and Measurement Technology Conference

作者： Sunil R. Das Danny L. Shaw Satyendra N. Biswas Mansour H. Assaf Scott Morton Irem Ozkarahan Emil M. Petriu Voicu Groza Department of Computer Science College of Arts and Sciences Troy University Montgomery AL 36103 USA School of Engineering and Computer Science Independent University Dhaka 1329 Bangladesh Department of Electrical and Electronic Engineering University of the South Pacific Suva Fiji School of Information Technology and Engineering Faculty of Engineering University of Ottawa Ottawa ON K1N 6N5 Canada

ISBN: (纸本)9781467346214

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TWO-INPUT LINEAR CASCADE IN SPACE COMPRESSION

TWO-INPUT LINEAR CASCADE IN SPACE COMPRESSION

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29th Annual IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

作者： Das, Sunil R. Applegate, Alexander R. Biswas, Satyendra N. Assaf, Mansour H. Groza, Voicu Petriu, Emil M. Troy Univ Coll Arts & Sci Dept Comp Sci Montgomery AL 36103 USA Univ Ottawa Fac Engn Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada Univ South Pacific Fac Sci & Technol Suva Fiji

ISBN: (纸本)9781457717710

Synthesizing aliasing-free space compactor for built-in self-testing of very large scale integration circuits and systems is of great importance, especially because of the design paradigm shift in recent years from system-on-board to system-on-chip. This paper investigates and provides additional results on a recently developed approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input XOR/XNOR logic. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems (ISCAS 85) combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the importance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.

关键词： Aliasing-free space compaction ATALANTA built-in self-testing in very large scale integration circuits and systems fault detection and conditional fault detection compatibility FSIM system-on-chips

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Cascade of two-input nonlinear logic in designing space compression networks in VLSI

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WORLD JOURNAL OF ENGINEERING 2012年第3期9卷 199-206页

作者： Das, Sunil R. Biswas, Satyendra N. Groza, Voicu Assaf, Mansour H. Univ Ottawa Fac Engn Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada Troy Univ Coll Arts & Sci Dept Comp Sci Montgomery AL 36103 USA Independent Univ Sch Engn & Comp Sci Dhaka 1329 Bangladesh USP Fac Sci & Technol Suva Fiji

Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults. For a pair of response outputs of the circuit under test, the method uses the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits (results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.

关键词： Aliasing-free space compaction ATALANTA Built-in self-testing in very large scale integration fault detection and conditional fault detection compatibility FSIM

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Cascade of Two-Input Nonlinear Logic in Designing Space Compression Networks in VLSI

Cascade of Two-Input Nonlinear Logic in Designing Space Comp...

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IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

作者： Das, Sunil R. Hossain, Altaf Groza, Voicu Assaf, Mansour H. Univ Ottawa Fac Engn Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada Univ Troy Coll Arts & Sci Dept Comp Sci Montgomery AL 36103 USA Univ South Pacific Sch Engn & Phys Fac Sci & Technol Suva Fiji

ISBN: (纸本)9781424479351

Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, utilizing well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method uses the notion of fault detection compatibility and conditional fault detection compatibility ( conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits ( results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.

关键词： Aliasing-free space compaction ATALANTA built-in self-testing in very large scale integration fault detection and conditional fault detection compatibility FSIM system-on-chips

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