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Checking before output may not be enough against fault-based cryptanalysis

IEEE TRANSACTIONS ON COMPUTERS 2000年第9期49卷 967-970页

作者： Yen, SM Joye, M Natl Cent Univ Dept Comp Sci & Informat Engn LCIS Chungli 320 Taiwan Gemplus Card Int Card Secur Grp F-13881 Gemenos France

In order to avoid fault-based attacks on cryptographic security modules (e.g., smart-cards), some authors suggest that the computation results should be checked for faults before being transmitted. In this paper, we describe a potential fault-based attack where key hits leak only through the information whether the device produces a correct answer after a temporary fault or not. This information is available to the adversary even if a check is performed before output.

关键词： cryptography exponentiation fault-based cryptanalysis tamper resistance interleaved modular multiplication

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Concurrent error detection in semi-systolic dual basis multiplier over GF(2^m) using self-checking alternating logic

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IET CIRCUITS DEVICES & SYSTEMS 2010年第5期4卷 382-391页

作者： Chiou, C. W. Liang, W. -Y. Chang, H. W. Lin, J. -M. Lee, C. -Y. Ching Yun Univ Dept Comp Sci & Informat Engn Chungli 320 Taiwan Natl Taipei Univ Technol Dept Comp Sci & Informat Engn Taipei 106 Taiwan Feng Chia Univ Dept Informat Engn & Comp Sci Taichung 407 Taiwan Lunghwa Univ Sci & Technol Dept Comp Informat & Network Engn Tao Yuan 333 Taiwan

Multiplication is one of the most important finite field arithmetic operations in cryptographic computations. Recently, the attacks of fault-based cryptanalysis have been a critical threat to both symmetrical and asymmetrical cryptosystems. To prevent such kind of attacks, masking faulty signals and outputting only correct ciphers would be a feasible solution, especially suitable for finite field multiplication. Therefore a novel dual basis multiplier in GF(2(m)) with concurrent error detection capability using self-checking alternating logic is presented. The new self-checking alternating logic dual basis multiplier saves about 67% space complexity as compared with other existing dual basis multiplier with concurrent error detection capability that uses the parity checking method. The proposed dual basis multiplier takes almost as low as one extra clock cycle to achieve concurrent error detection capability. Furthermore, any existing faults in fault model are ensured to be detectable through at least one input in the authors' proposed scheme.

关键词： fault-based cryptanalysis semisystolic dual basis multiplier finite field arithmetic operation self-checking alternating logic systolic arrays digital arithmetic parity checking concurrent error detection finite field multiplication clock cycle faulty signal masking cryptographic computation asymmetrical cryptosystem fault diagnosis cryptography clocks circuit complexity Galois fields fault model multiplying circuits space complexity

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On the implementation of public key cryptosystems against fault-based attacks

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1999年第6期E82A卷 1082-1089页

作者： Laih, CS Tu, FK Lee, YC Natl Cheng Kung Univ Dept Elect Engn Commun Lab Tainan 70101 Taiwan

Secret information stored in a tamperfree device is revealed during the decryption or signature generation processes due to fault-based attack. In this paper, based on the coding approach, we propose a new fault-resistant system which enables any fault existing in modular multiplication and exponentiation computations to be detected with a very high probability. The proposed method can be used to implement all crypto-schemes whose basic operations are modular multiplications for resisting: both memory and computational fault-based attacks with a very low computational overhead.

关键词： fault-based cryptanalysis error detection modular multiplication tamperfree devices arithmetic codes cryptosystems

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Concurrent error detection and correction in a polynomial basis multiplier over GF(2^m)

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IET INFORMATION SECURITY 2010年第3期4卷 111-124页

作者： Huang, W-T Chang, C. H. Chiou, C. W. Chou, F. H. Minghsin Univ Sci & Technol Dept Comp Sci & Informat Engn Hsinchu 30401 Taiwan Natl Taipei Univ Technol Inst Comp & Commun Taipei 106 Taiwan Ching Yun Univ Dept Comp Sci & Informat Engn Chungli 320 Taiwan Ching Yun Univ Dept Elect Engn Chungli 320 Taiwan

Finite-field arithmetic has been widely used to speed up the encryption and decryption processes in many cryptosystems, especially elliptic curve cryptosystems. Regular finite-field arithmetic structures are suitable for very large-scale integration implementation of cryptosystems, making them attractive for mobile commerce applications. Multiplication is the critical operation in finite-field arithmetic operations. fault-based cryptanalysis is a new cryptanalysis method that deliberately injects faults into cryptographic devices, and requires only a small amount of side-channel information to break common ciphers. Thus, effective and simple methods for protecting the encryption/decryption circuitry from attackers are required to ensure that cryptographic devices can produce accurate signatures. This study presents a polynomial basis (PB) multiplier over GF(2(m)) with concurrent error detection (CED), and proposes a PB multiplier with concurrent error correction (CEC). A parallel structure of function cells is used in the proposed multiplier array to reduce the propagation delay. The proposed PB multiplier with internal parallel structure can reduce the time complexity by 28%, and reduce the space complexity by 90%, compared with existing PB multipliers. Compared with existing PB multipliers with CED, the proposed device with CED has a 20% greater space complexity but a 30% less time complexity. To the author's knowledge, there is no previous report of PB multipliers with CEC capability. The proposed PB multiplier with CEC capability has a space complexity of only about 10% more and requires five more clock cycles than the proposed device without CEC capability.

关键词： fault-based cryptanalysis function cell parallel structure mobile commerce applications polynomials finite-field arithmetic public key cryptography Cryptography digital arithmetic decryption process Algebra Digital arithmetic methods cryptographic devices elliptic curve cryptosystems Digital electronics concurrent error correction Data security encryption process side-channel information concurrent error detection polynomial basis multiplier

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fault-tolerant Gaussian normal basis multiplier over GF(2^m)

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IET INFORMATION SECURITY 2012年第3期6卷 157-170页

作者： Chuang, T. -P. Chiou, C. Wun Lin, S. -S. Lee, C. -Y. Natl Taiwan Normal Univ Dept Comp Sci & Informat Engn Taipei 116 Taiwan Ching Yun Univ Dept Comp Sci & Informat Engn Chungli 320 Taiwan Lunghwa Univ Dept Comp Informat & Network Engn Gueishan 333 Taoyuan County Taiwan

fault-tolerant design of a finite field multiplier is an efficient method for resisting fault-based cryptanalysis in Elliptic curve cryptosystems. A novel fault-tolerant bit-parallel Gaussian normal basis (GNB) multiplier with type-t over GF(2(m)), which can tolerate multiple module failures at one time, is presented. No hardware modification in the proposed GNB multiplier is required to achieve the fault-tolerant function. Hence, the proposed fault-tolerant GNB multiplier has low hardware cost. The reliability of the proposed fault-tolerant GNB multiplier with type-t increases as t increases. However, the behaviour of existing GNB multipliers with concurrent error correction (CEC) resembles triple modular redundancy (TRM) when t > 3. In practice, most of suggested m's by NIST use GNB with type-t > 3. The proposed fault-tolerant GNB multiplier is an N-modular redundancy (NMR) system with N = t. Thus, the proposed fault-tolerant GNB multiplier with type-t can tolerate at most t/2-1 failed modules simultaneously, while existing GNB multipliers with CEC only can tolerate one failed module. The proposed GNB multiplier requires less extra space and time complexities than similar multipliers. System reliability of the proposed fault-tolerant GNB multiplier is better than that of similar GNB multipliers.

关键词： GF(2m) space complexities fault-based cryptanalysis fault-tolerant bit-parallel Gaussian normal basis multiplier finite field multiplier TRM fault tolerant computing GNB public key cryptography Cryptography CEC Gaussian processes fault-tolerant design triple modular redundancy n-modular redundancy system Computational complexity time complexities elliptic curve cryptosystems computational complexity NMR Data security hardware modification Other topics in statistics concurrent error correction

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Attacking right-to-left modular exponentiation with timely random faults

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3rd International Workshop on fault Diagnosis and Tolerance in Cryptography

作者： Boreale, Michele Univ Florence Dipartimento Sistemi & Informat I-50134 Florence Italy

ISBN: (纸本)3540462503

We show that timely induction of random failures can potentially be used to mount very cost effective attacks against smartcards deploying cryptographic schemes based on (right-to-left) modular exponentiation. We introduce a model where an external perturbation, or glitch, may cause a single modular multiplication to produce a truly random result. based on this assumption, we present a probabilistic attack against the implemented cryptosystem. Under reasonable assumptions, we prove that using a single faulty signature the attack recovers a target bit of the secret exponent with an error probability bounded by 3/7. We show the attack is effective even in the presence of message blinding.

关键词： fault-based cryptanalysis smartcards public-key cryptosystems

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Parametric Trojans for fault-Injection Attacks on Cryptographic Hardware 11

Parametric Trojans for Fault-Injection Attacks on Cryptograp...

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11th Workshop on fault Diagnosis and Tolerance in Cryptography (FDTC)

作者： Kumar, Raghavan Jovanovic, Philipp Burleson, Wayne Polian, Ilia Univ Massachusetts Amherst MA 01002 USA Univ Passau D-94032 Passau Germany

ISBN: (纸本)9781479962921

We propose two extremely stealthy hardware Trojans that facilitate fault-injection attacks in cryptographic blocks. The Trojans are carefully inserted to modify the electrical characteristics of predetermined transistors in a circuit by altering parameters such as doping concentration and dopant area. These Trojans are activated with very low probability under the presence of a slightly reduced supply voltage (0.001 for 20% V-dd reduction). We demonstrate the effectiveness of the Trojans by utilizing them to inject faults into an ASIC implementation of the recently introduced lightweight cipher PRINCE. Full circuit-level simulation followed by differential cryptanalysis demonstrate that the secret key can be reconstructed after around 5 fault-injections.

关键词： fault-based cryptanalysis fault injection hardware Trojans

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fault-based Attacks on the Bel-T Block Cipher Family

Fault-based Attacks on the Bel-T Block Cipher Family

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Conference on Design Automation Test in Europe (DATE)

作者： Jovanovic, Philipp Polian, Ilia Univ Passau D-94032 Passau Germany

ISBN: (纸本)9783981537048

We present the first fault-based attack on the Bel-T block cipher family which has been adopted recently as a national standard of the Republic of Belarus. Our attack successfully recovers the secret key of the 128-bit, 192-bit and 256-bit versions of Bel-T using 4, 7 and 10 fault injections, respectively. We also show the results from our comprehensive simulation-based experiments.

关键词： fault-based cryptanalysis fault injection block cipher

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