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Bilinear Double-Order Filter Designs and Application Examples

IEEE ACCESS 2024年 12卷 14040-14049页

作者： Nako, Julia Psychalinos, Costas Khateb, Fabian Elwakil, Ahmed S. Univ Patras Elect Lab Dept Phys Patras 26504 Greece Brno Univ Technol Dept Microelect Brno 60190 Czech Republic Czech Tech Univ Fac Biomed Engn Kladno 27201 Czech Republic Univ Def Dept Elect Engn Brno 66210 Czech Republic Univ Sharjah Dept Elect Engn Sharjah U Arab Emirates Univ Calgary Dept Elect & Software Engn Alberta AB T2N 1N4 Canada Nile Univ Nanoelect Integrated Syst Ctr NISC Giza 12677 Egypt

A novel kind of non-integer order bilinear filters, named double-order bilinear filters, is introduced in this work. They are based on the employment of two non-integer orders, offering the maximum design flexibility in comparison with their fractional-order and power-law counterparts. An attractive offered benefit is that this is achieved without increasing the circuit complexity, since the proposed structure is capable of realizing all non-integer kinds of filters. Two design examples are provided, where it is shown that lead/lag compensators utilized in control applications and low/high shelving filters employed in acoustic applications are actually bilinear filters with suitably selected pole/zero frequencies. Simulation and experimental results, using the OrCAD PSpice simulator and a field programmable analog array device, respectively, support the findings of this work.

关键词： Information filters Nonlinear filters Maximum likelihood detection Behavioral sciences Poles and zeros High frequency field programmable analog arrays Filters analog filters bilinear filters compensators curve-fitting approximation field programmable analog array fractional-order filters power-law filters shelving filters

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Approximation of complex coefficient filters

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2025年 197卷

作者： Nako, Julia Tsirimokou, Georgia Psychalinos, Costas Elwakil, Ahmed S. Univ Patras Dept Phys Elect Lab GR-26504 Patras Greece Univ Ioannina Dept Comp Sci & Engn GR-45110 Ioannina Greece Univ Sharjah Dept Elect Engn POB 27272 Sharjah U Arab Emirates Nile Univ Nanoelect Integrated Syst Ctr NISC Giza Egypt Univ Calgary Dept Elect & Software Engn Calgary AB Canada

This work presents approximations of two classes of complex filters, those with complex poles only and those with both complex poles and zeros. The approximation of these complex coefficient filter is based on a curve-fitting technique, where the magnitude response of the filters is approximated to a rational integer-order transfer function. The proposed approximation method is validated through MATLAB simulations and is experimentally verified using a field programmable analog array (FPAA) device, which offers digital programmability.

关键词： Complex filters Complex coefficient transfer functions analog filters analog signal processing field programmable analog array

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Design of Complex-Order PI/PID Speed Controllers and its FPAA Realization

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IEEE ACCESS 2023年 11卷 118606-118614页

作者： George, Mary Ann Elwakil, Ahmed S. Allagui, Anis Psychalinos, Costas Manipal Acad Higher Educ MAHE Sch Engn & IT Dubai U Arab Emirates Univ Sharjah Res Inst Sci & Engn Ctr Adv Mat Res Sharjah U Arab Emirates Univ Sharjah Dept Elect & Comp Engn Sharjah U Arab Emirates Nile Univ Nanoelect Integrated Syst Ctr NISC Giza 12677 Egypt Univ Calgary Dept Elect & Software Engn Alberta AB T2N 1N4 Canada Univ Sharjah Dept Sustainable & Renewable Energy Engn Sharjah U Arab Emirates Florida Int Univ Dept Mech & Mat Engn Miami FL 33174 USA Univ Patras Dept Phys Elect Lab Patras 26504 Greece

Complex-order controllers are a generalized version of conventional integer-order controllers and are known to offer greater flexibility, better robustness, and improved system performance. This paper discusses the design of complex-order PI/PID controllers to control the speed of an induction motor drive and an electric vehicle. The speed-tracking performance of the complex-order controllers is compared with fractional-order controllers and conventional integer-order controllers. Implementing complex-order controllers is challenging due to commercial complex-order fractance element unavailability. Hence, it is carried out by approximating the complex-order controller transfer function using an integer-order rational function with a curve-fitting approach, namely the Sanathanan Koener (SK) iterative method. This method is quite simple and can fit the required frequency range compared to the conventional Matsuda and Oustaloup approaches. The approximated controller transfer function can easily be realized by employing the AN231E04 field programmable analog array (FPAA). Simulation and experimental results highlight that the controller behaviour is in good agreement with the theoretical expectations.

关键词： Complex-order controllers speed control field programmable analog array fractional-order systems

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A study on Implementation of the Motor Neuron in the Swimming Pattern Generator of a Lamprey 31

A study on Implementation of the Motor Neuron in the Swimmin...

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31st IEEE Conference on Signal Processing and Communications Applications (SIU)

作者： Korkmaz, Nimet Kayseri Univ Merkez Kampusu Elekt Elekt Muhendisligi Bolumu Kayseri Turkiye

ISBN: (纸本)9798350343557

The numerical simulations and hardware realizations of the structures, which are inspired by central pattern generator networks and characterized as biologically inspired systems, draw attention. Numerical simulations of these structures are important in examining the characteristics of these systems. However, the studies about the hardware realizations of the central pattern generator structures also appear as an alternative research area for the applications where real-time electrical signals are required. In this study, after the examination of the central pattern generator network, which are proposed for the swimming movement control of the lamprey, the hardware implementation of the motor neuron identification in this network structure is performed. The field programmable analog array (FPAA) element is used in the implementation process and the FPAA device draws attention with its low hardware cost, rapid prototyping and reconfiguration features.

关键词： swimming central pattern generator field programmable analog array lamprey neuron

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A systematic approach for the design of linear filters and oscillators employing tree representation

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analog INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2021年第1期108卷 181-203页

作者： Datta, Debanjana Bhanja, Mousumi Banerjee, Ayan Ray, Baidyanath Indian Inst Engn Sci & Technol IIEST Dept Elect & Telecommun Engn ETCE Howrah 711103 W Bengal India Pailan Coll Management & Technol Dept ECE Kolkata W Bengal India

In this paper, a block based systematic approach for synchronous design of linear filters and oscillators through full design space exploration is presented, which exploits inherent hierarchical property of tree. To bridge the gap between system specification and hardware structure of analog system, transfer function of linear filter and characteristic equation of oscillator have been modeled using a rooted tree, formed based on the characteristics of four basic building blocks. A hardware conversion algorithm has been used to map the paths of the tree into operational transconductance amplifier (OTA) based circuits, implementing both programmable linear filter and oscillator. Twenty seven distinct architectures for filters and oscillators are generated. The proposed approach is also compatible with field programmable analog array (FPAA), as demonstrated by mapping the generated circuits into a hexagonal FPAA.

关键词： Linear filter Oscillator Operational transconductance amplifier Biquadratic structure field programmable analog array

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A Reconfigurable and Compact Spin-Based analog Block for Generalizable nth Power and Root Computation 20

A Reconfigurable and Compact Spin-Based Analog Block for Gen...

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20th IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Tatulian, Adrian DeMara, Ronald F. Univ Cent Florida Dept Elect & Comp Engn Orlando FL 32816 USA

ISBN: (纸本)9781665439466

While square and square root are critical for vector operations, several challenges exist in their computation in the digital domain including power, area, and delay overheads. While selective computation in the analog domain is a longstanding alternative, tradeoffs of increased noise and reduced accuracy are prominent challenges. Herein, we propose a reconfigurable analog circuit which is capable of performing any nth-power and nth-root function and may be implemented within an analog or mixed-signal field programmable array. The resulting analog block of Magnetic Tunnel Junctions (MTJs) along with FET-based sensing and amplification circuits are circuit-switched-configurable with terminal-level control. Herein the design is configured to rapidly evaluate various arithmetic operations within acceptable error tolerances for selected applications. When compared to a state-of-the-art approximate digital multiplier, our design yields 97% reduction in transistor count and stable output within a period comparable to single-cycle execution. When compared to an alternative recently proposed analog multiplier, the proposed design yields improvement in error and versatility to perform generalized operations.

关键词： analog computation reconfigurable computing field programmable analog array Magnetic Tunnel Junction

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Random Number Generator Based on Skew-tent Map and Chaotic Sampling 16

Random Number Generator Based on Skew-tent Map and Chaotic S...

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16th IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS) / IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

作者： Ergun, Salih Tanriseven, Sercan ERGTECH Res Ctr Zurich Switzerland

ISBN: (纸本)9781728193960

In this paper a novel random number generator is introduced and it is based on the Skew-tent discrete-time chaotic map. The RNG presented in this paper is made using the discrete-time chaotic map and chaotic sampling of regular waveform method together to increase the throughput and statistical quality of the output sequence. An explanation of the arithmetic model for the proposed design is given in this paper with an algebra confirmation for the generated bit stream that shows how it passes the primary four tests of the FIPS-140-2 test suit successfully. Finally the bit stream resulting from the hardware implementation of the circuit in a similar method has been confirmed to pass all NIST-800-22 test with no post processing. A presentation of the experimentally obtained results is given therefor proving the the circuit's usefulness. The proposed RNG can be built with the integrated circuit.

关键词： cryptography random number generator chaotic sampling of regular waveform field programmable analog array skew-tent map discrete-time chaos

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Development of a XYZ scanner for home-made atomic force microscope based on FPAA control

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MECHANICAL SYSTEMS AND SIGNAL PROCESSING 2019年 131卷 222-242页

作者： Tian, Yanling Cai, Kunhai Zhang, Dawei Liu, Xianping Wang, Fujun Shirinzadeh, Bijan Tianjin Univ Key Lab Mech Theory & Equipment Design Minist Educ Tianjin 300072 Peoples R China Univ Warwick Sch Engn Coventry CV4 7AL W Midlands England Monash Univ Dept Mech & Aerosp Engn Robot & Mechatron Res Lab Clayton Vic 3800 Australia

Atomic force microscopy (AFM) is one of the useful tools in the fields of nanoscale measurement and manipulation. High speed scanning is one of the crucial requirements for live cell imaging and soft matter characterization. The scanning speed is limited by the bandwidth of the AFM's detection and actuation components. Generally, the bandwidth of a traditional scanner is too low to conduct the live cell imaging. This paper presents a simple and integrated compact home-made AFM for high speed imaging. To improve the bandwidth of the scanner, a parallel kinematics mechanism driven by piezoelectric actuators (PZTs) is proposed for the fast positioning in the X, Y and Z directions. The mechanical design optimization, modeling and analysis, and experimental testing have been conducted to validate the performance of the proposed scanner. A number of experimental results showed that the developed scanner has the capability for broad bandwidth with low coupling errors in the actuation directions. A hybrid control strategy including feedforward and feedback loops has been designed to significantly improve the dynamic tracking performance of the scanner and a field programmable analog array (FPAA) system is utilized to implement the control algorithm for excellent and stable tracking capability. Further, a number of high speed measurements have been conducted to verify the performance of the developed AFM. (C) 2019 Elsevier Ltd. All rights reserved.

关键词： XYZ scanner field programmable analog array Home-made AFM High speed scanning

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LOW VOLTAGE CURRENT CONVEYOR-BASED field programmable analog array

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2011年第8期20卷 1677-1701页

作者： Mahmoud, Soliman A. Soliman, Eman A. Sharjah Univ Elect & Comp Engn Dept Sharjah Univ City 27272 Sharjah U Arab Emirates Fayoum Univ Dept Elect Engn Al Fayyum Egypt German Univ Cairo Elect & Elect Engn Dept Cairo 11835 Egypt

In this paper a low voltage low power field programmable analog array (FPAA) is realized. The FPAA configurable analog block (CAB) design is based on three-bit digitally controlled fully differential current conveyor. The FPAA consists of seven CABs. The CABs are directly connected together without adding extra hardware by placing them in a hexagonal lattice arrangement. A variable gain amplifier, tunable second-order low-pass filter, and a tunable second-order band-pass filter are realized as an application for the FPAA. The FPAA total power consumption is 105.12 mW at 1V supply. The FPAA is realized using IBM 90 nm CMOS technology model from MOSIS under voltage supply of +/- 0.5 V.

关键词： Configurable analog block current division network digitally controlled fully differential current conveyor field programmable analog array tunable band-pass filter tunable low-pass filter variable gain amplifier

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Random Number Generation Using Dual Oscillator Architecture and Discrete-Time Chaos

Random Number Generation Using Dual Oscillator Architecture ...

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International Symposium on Electronics and Smart Devices (ISESD) - Smart Devices for Big Data Analytic and Machine Learning

作者： Ergun, Salih Tanriseven, Sercan ERGTECH Res Ctr Zurich Switzerland

ISBN: (纸本)9781538666708

This paper introduces a novel random number generator which is based on Bernoulli discrete-time chaotic map. In order to boost the throughput and to increase the statistical quality of the output sequence, presented RNG is designed using the discrete-time chaotic map together with the dual oscillator architecture. An arithmetic model of the suggested design had been elaborated and it has been algebraically confirmed that the generated bit stream has successfully passed all four primary tests of the FIPS-140-2 test suite. Lastly, it has also been confirmed that the bit stream, which was obtained from the hardware realization of the circuit in a similar way, has passed all the NIST-800-22 tests without any post-processing. The results obtained from the experiment and simulation, which confirm the usefulness of the circuit, are presented. We can build the suggested RNG using the integrated circuit.

关键词： discrete-time chaos random number generator bernoulli map dual oscillator architecture cryptography field programmable analog array

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