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IEEE International Conference on Computer and Information

作者： Bai, Yu Lin, Mingjie IEEE United States

ISBN: (纸本)9781509001545

This paper presents a probabilistic-based design methodology for a random number generator according to any given probability density function. Our basic idea is to perform massively parallel analog computation through Gaussian mixture modelling. There are two main contributions in this work. First, we developed a new approach to performing Gaussian mixture decomposition with simple analog circuits. Second, we have presented a novel methodology to exploit the stochastic switching behavior of Magnetic Tunneling Junction (MTJ) as a hardware-efficient Gaussian noise generator. Our resulting universal random number generator not only achieves extremely low energy consumption and ultra-high computing performance, but also is highly reconfigurable. Consequently, it can be widely applicable in many hardware-based signal processing applications, especially quite useful in the newly emerging stochastic-based computing systems. Finally, to validate our design, we used field-programmable analog array to implement all required components.

关键词： field-programmable analog array Magnetic Tunneling Junction (MTJ) Universal Random Number Generation

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Universal Random Number Generation with field-programmable analog array and Magnetic Tunneling Junction (MTJ) Devices

Universal Random Number Generation with Field-Programmable A...

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IEEE International Conference on Ubiquitous Computing and Communications

作者： Yu Bai Mingjie Lin Department of Electrical Engineering Eindhoven University of Technology Eindhoven The Netherlands

ISBN: (纸本)9781509001552

关键词： Universal Random Number Generation field-programmable analog array Magnetic Tunneling Junction (MTJ) Devices

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Design and analysis of a dual mode CMOS field programmable analog array

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Journal of Semiconductors 2014年第10期35卷 152-162页

作者：程小燕杨海钢尹韬吴其松张洪锋刘飞 Institute of Electronics Chinese Academy of Sciences University of Chinese Academy of Sciences

This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.

关键词： field-programmable gate array field-programmable analog array configurable analog block rail-to- rail biquadratic filters

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Elementary Negative Group Delay Filter Functions

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2024年第6期43卷 3396-3409页

作者： Nako, Julia Psychalinos, Costas Maundy, Brent J. Elwakil, Ahmed S. Univ Patras Dept Phys Elect Lab Rion 26504 Patras Greece Univ Calgary Dept Elect & Software Engn Calgary AB Canada Univ Sharjah Dept Elect Engn POB 27272 Sharjah U Arab Emirates Nile Univ Nanoelect Integrated Syst Ctr NISC Giza Egypt

A theoretical study of the behavior of some elementary first- and second-order functions, which are suitable for realizing negative group delay, is performed in this work. As both the gain and phase responses are simultaneously considered, important derivations related to the actual bandwidth of operation are derived accompanied by useful design tips. The presented theory is supported by simulation and experimental results obtained through the utilization of typical active-RC filter structures, as well as from a field-programmable analog array device.

关键词： Negative group delay filters analog signal processing analog filters Bilinear filters Inverse filters field-programmable analog array

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Realizations of fractional-order PID loop-shaping controller for mechatronic applications

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INTEGRATION-THE VLSI JOURNAL 2021年 80卷 5-12页

作者： Kapoulea, Stavroula Psychalinos, Costas Elwakil, Ahmed S. HosseinNia, S. Hassan Univ Patras Dept Phys Elect Lab GR-26504 Patras Greece Univ Sharjah Dept Elect & Comp Engn POB 27272 Sharjah U Arab Emirates Nile Univ Nanoelect Integrated Syst Ctr NISC Giza Egypt Univ Calgary Dept Elect & Comp Engn Calgary AB Canada Delft Univ Technol Dept Precis & Microsyst Engn PME NL-2628 CD Delft Netherlands

A novel procedure for the realization of a fractional-order PID loop-shaping controller, suitable for precision control of mechatronic systems, is introduced in this work. Exploiting appropriate tools, the controller function is approximated as a whole, leading to a simple form of integer-order approximation, when compared to the case where each intermediate part of the PID transfer function is approximated. This leads to a direct implementation, composed of conventional active and passive elements. Simulation and experimental results, derived from the OrCAD PSpice simulator and a field-programmable analog array respectively, verify the efficient functionality of the proposed implementation procedure.

关键词： Mechatronics Fractional-order PID controller Curve-fitting approximation technique Pade approximation field-programmable analog array

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On the Realization of Power-Law Based Impedance Functions: Application to Edible Drinks 10

On the Realization of Power-Law Based Impedance Functions: A...

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10th International Conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Kapoulea, Stavroula Psychalinos, Costas Elwakil, Ahmed S. Univ Patras Phys Dept Elect Lab Rion Greece Univ Sharjah Dept Elect & Comp Engn Coll Engn Sharjah U Arab Emirates

ISBN: (纸本)9781665418478

A novel procedure for compact realization of complex, multiple-parameter impedance functions is introduced in this paper. The concept is based on the consideration of the whole impedance function and the approximation of its frequency characteristics through a suitable curve-fitting-based algorithm, instead of separately approximating the intermediate terms of the function. In this way, the total impedance is implemented by a topology which is based on one transfer function, offering the benefit of reduced complexity. The impedance function that describes the electrical properties of edible drinks can be considered as a characteristic example and, therefore, is used for the verification of the proposed concept. Different samples of drinks, red wine from Bairrada, semi-skimmed and organic semi-skimmed milk, are considered with the behavior of the proposed schemes being evaluated through simulation and experimental results.

关键词： electrical impedance spectroscopy electrical bio-impedance models fractional-order impedance power-law transfer functions curve-fitting approximation field-programmable analog array

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Simple implementations of fractional-order driving-point impedances: Application to biological tissue models

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2021年 137卷 153784-153784页

作者： Kapoulea, Stavroula Psychalinos, Costas Elwakil, Ahmed S. Univ Patras Dept Phys Elect Lab GR-26504 Patras Greece Univ Sharjah Dept Elect & Comp Engn POB 27272 Sharjah U Arab Emirates Nile Univ Nanoelect Integrated Syst Ctr NISC Giza Egypt Univ Calgary Dept Elect & Comp Engn Calgary AB Canada

A novel procedure for the circuit implementation of the driving-point impedance of frequency-domain material models, constructed from fractional-order elements of arbitrary type and order, is introduced in this work. Following this newly introduced concept, instead of emulating separately each fractional-order element in the model under consideration, the direct emulation of the complete model can be achieved through the approximation of the total impedance function. The magnitude and phase frequency responses of the impedance function are first extracted and approximated through curve-fitting-based techniques. A rational integer-order driving-point impedance function is then obtained and realized using appropriately configured passive and/or active topologies. Comparison between the conventional method and the proposed method reveals that the achieved benefit is the significant reduction of the passive and/or active components count. Verification of the introduced concept is performed through circuit simulation results using OrCAD PSpice in the case of a root/ stem/electrode interface model, as well as through experimental results where the driving-point input impedance of the human respiratory system under different health conditions is synthesized on a field-programmable analog array device.

关键词： Bio-impedance Fractional-order impedance Electrical Impedance Spectroscopy Fractional-order capacitor Fractional-order inductor Curve-fitting techniques field-programmable analog array

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New alternatives for analog implementation of fractional-order integrators, differentiators and PID controllers based on integer-order integrators

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NONLINEAR DYNAMICS 2017年第1期90卷 241-256页

作者： Muniz-Montero, Carlos Garcia-Jimenez, Luis V. Sanchez-Gaspariano, Luis A. Sanchez-Lopez, Carlos Gonzalez-Diaz, Victor R. Tlelo-Cuautle, Esteban Univ Politecn Puebla Elect & Telecommun Dept Puebla 72640 Mexico Benemerita Univ Autonoma Puebla Fac Elect Puebla 72592 Mexico Univ Autonoma Tlaxcala Dept Elect Apizaco 90300 Tlaxcala Mexico INAOE Dept Elect Puebla 72840 Mexico CINVESTAV Comp Dept Mexico City 07360 DF Mexico

In this work, we propose an alternative for the circuital realization of analog fractional-order differentiators and integrators without using ladder networks. This alternative is obtained by a mathematical manipulation of a rational function in a similar way to the reported for the synthesis of the variable-state filters. The advantage of the proposed implementation is the requirement of only simple analog design blocks, such as integrators (of integer order), differential amplifiers and two-input adder amplifiers. Most important, contrarily to other reported solutions, the proposed realization can be fulfilled using commercially available resistors and capacitors, with a reduced number of calculations, and without negative impedance converters or inductors. In addition, the orders of the fractional derivative and integral can be modified just varying the gain of the differential amplifiers and adders. To validate the proposal of implementation, and as example of application, we present simulations (HSPICE, MATLAB) and experimental results of a first-order plus dead time plant controlled by fractional-order PI and PID controllers. The experimental results were obtained from a realization using field-programmable analog arrays. A comparison analysis highlights that the proposed alternative of implementation presents advantages regarding a Cauer-network-based realization in terms of number of active and passive elements, number of passive elements with non-commercial available values and design complexity.

关键词： Fractional calculus Fractional-order PID controllers field-programmable analog array

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Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2017年第7期36卷 2672-2696页

作者： Szczesny, Szymon Poznan Univ Tech Fac Comp Chair Comp Engn Piotrowo 3A St PL-61138 Poznan Poland

This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital-analog converter, an elliptic filter with SNR40.42 dB, 2D-DCT processor with PSNR53.05 dB and RGB-to-YCrCb converter with PSNR46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.

关键词： field-programmable analog array Common mode rejection ratio Signal processing Image processing Current mirror Mismatch

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RAMP: Accelerating Wireless Sensor Hardware Design with a Reconfigurable analog/Mixed-Signal Platform 14

RAMP: Accelerating Wireless Sensor Hardware Design with a Re...

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14th IEEE/ACM International Conference on Information Processing in Sensor Networks (IPSN)

作者： Kelly, Brandon M. Rumberg, Brandon Graham, David W. Kulathumani, Vinod Clites, Spencer Dilello, Alex Navidi, Mir Mohammad West Virginia Univ Lane Dept Comp Sci & Elect Engn Morgantown WV 26506 USA

ISBN: (纸本)9781450334754

To meet the demanding requirements in the growing area of wireless sensing applications, some sensing platforms have included low-power application-specific hardware to process the sensor data for compression and pre-classification of the relevant information. While this additional hardware can reduce the overall power consumption of the system, a unique hardware solution is required for each application. To diminish this burden, we will demonstrate a reconfigurable analog/mixed-signal sensing platform. At the hardware-level, this platform consists of a reconfigurable integrated circuit containing many commonly used circuit components that can be connected in any configuration to perform sensor interfacing and ultra-low-power signal processing. At the software level, this platform provides a framework for abstracting the underlying hardware. We will demonstrate how our platform allows a developer to create applications ranging from standard sensor interfacing techniques to more complicated intelligent pre-processing and wake-up detection, without the necessity of circuit-level expertise.

关键词： analog Signal Processing field-programmable analog array Energy-Efficient In-Network Processing Sensor Networks

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