Boundary scan is a widely adopted DFT (Design For Test). According to the characteristic of FPGA application, this paper presents a boundary scan circuit designed for FDEGA (field-programmabledatapathenhancedgate A...
详细信息
ISBN:
(纸本)078037889X
Boundary scan is a widely adopted DFT (Design For Test). According to the characteristic of FPGA application, this paper presents a boundary scan circuit designed for FDEGA (field-programmable datapath enhanced gate array), an FPGA new architecture of our group. This design emphasizes the function of PCB level test while considering chip level test function as well. We also integrate device-programming function into the circuit. In implementation of our design, "single DFF (D Flip-Flop) chain" structure is adopted to decrease area consumption. We finished the layout design in 0.6um CMOS process and integrated it into our FDEGA chip. Test result of fabricated chip meets the design requirement, and shows that the circuit can achieve the expected test function and programming function while observing IEEE1149.1 standard.
作者：
Ma, XJTong, JRFudan Univ
Microelect Dept ASIC & Syst State Key Lab Shanghai 200433 Peoples R China
FPGA is widely applied in datapath applications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDE...
详细信息
ISBN:
(纸本)078037889X
FPGA is widely applied in datapath applications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDEGA (field-programmable datapath enhanced gate array). The LC of FDEGA is optimized for datapath implementation. and can be programmed as either combinational or sequential device. FDEGA has hierarchical interconnection architecture. A chip with 16*16 LC array has been fabricated, and the design of LC and interconnection has been tested, and circuit sample chosen from practical digital system design has been implemented in FDEGA. The result proves that our design of FDEGA is correct.
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