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Stability-guaranteed predictive sliding surface control of silicon carbide dual-output nine-switch inverter

ELECTRICAL ENGINEERING 2022年第4期104卷 2009-2020页

作者： Gulbudak, Ozan Karabuk Univ Coll Engn Dept Elect Elect Engn Main Campus Elect Elect Engn 108 TR-78050 Karabuk Turkey

In this study, a finite control set model predictive control strategy is proposed for a nine-switch converter system. The predictive control routine with discrete-solution space in energy transformation applications is widely used and offers a satisfactory closed-loop operation. However, the stability analysis of the predictive control method is a challenging task, and the practical stability approaches are applied to examine the closed-loop stability characteristics. Designing the guaranteed-stability predictive control is not an easy task since even the norm choice of the objective function may result in closed-loop instability. Regarding closed-loop stability, stability-guaranteed predictive sliding surface control approach is introduced in this study. The multi-objective cost function is reformulated in the proposed method as a sliding surface function usually used in sliding mode control methods. Thus, the best-suited control input that meets the sliding mode control stability criterion is picked. The proposed reformulation process enables the sliding surface function as an objective function, and the sliding surface function is gauged for each legitimate switching combination. The proposed control method is experimentally verified by using a 3.2 kW silicon carbide nine-switch inverter prototype. The experimental results prove that the proposed method guarantees closed-loop stability, and dual-AC load control is achieved.

关键词： Sliding mode control Sliding surface-based predictive approach Nine-switch inverter field-programmable gate array Nonlinear control

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FPGA-oriented Two-phase Bundled-data Circular Self-timed Pipeline 12

FPGA-oriented Two-phase Bundled-data Circular Self-timed Pip...

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12th International Symposium on Computing and Networking

作者： Yoshikawa, Senri Sannomiya, Shuji Iwata, Makoto Nishikawa, Hiroaki Univ Tsukuba Grad Sch Sci & Technol Tsukuba Ibaraki Japan Univ Tsukuba Inst Syst & Informat Engn Tsukuba Ibaraki Japan Kochi Univ Technol Sch Informat Kami Kochi Japan Univ Tsukuba Tsukuba Ibaraki Japan

ISBN: (纸本)9798331528379;9798331528362

Self-timed pipeline (STP) is an attractive circuit architecture because its local data transfer naturally realizes pipeline-stage-level signal gating and thus leads to high power-performance efficiency. A circular STP can realize not only iterative or recursive operations but also program execution. There exists a circuit configuration and its design procedure that make it possible to implement the circular STP on highly available commercial FPGAs, which provide flexibility at circuit level, by utilizing the standard EDA tool provided by the FPGAs' vendors;however, the existing configuration is premised on a data transfer manner called four-phase bundled-data, in which main transfer control signals transition four times when a set of data is transferred between adjacent pipeline stages. In this paper, we propose a circuit configuration for two-phase bundled-data manner that makes main transfer control signals transition only twice for transferring a data set and thus potentially leads to a higher throughput. The proposed configuration realizes the circular STP's basic functions: the merge of two pipelines into one, the branch of one pipeline to two, and the copy and/or erasure of a data set. To make it possible to apply the existing design procedure to the proposed configuration, we reveal intrinsic timing constraints exhaustively and present a timing information acquisition technique for static timing analysis. According to the proposed configuration, we implemented a circular STP on AMD Zynq-7000 FPGA. Based on the implementation, we demonstrate that the proposed configuration requires an approximately 15% larger circuit area and it can achieve the approximately 1.6 times higher maximum pipeline throughput in comparison with the existing four-phase bundled-data version.

关键词： two-phase bundled-data self-timed pipeline field-programmable gate array circular pipeline

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Efficient Co-Approximate Parallel Compressive Depth Reconstruction on FPGA

Efficient Co-Approximate Parallel Compressive Depth Reconstr...

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2025 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Wu, Yun McAllister, John School of Electrical Electronic and Computer Engineering Queen's University Belfast United Kingdom

ISBN: (纸本)9798350368741

Efficient depth image reconstruction from sparse samples is crucial for machine perception applications, such as robotics, vehicle assistance and autonomy. It demands fast processing speed with low power consumption for sensing quality and safety, as well as cost reduction for FPGA and solid state implementations, within constrained resource budgets on edge devices. A new co-approximate framework of parallel approximate compressive depth reconstruction engine on FPGA is proposed using 1 solvers, proximal gradient decent (PGD), with instrumented frequency and voltage scaling during the iterative optimization process. By evaluating various number of parallel approximate processing units for the depth image reconstruction engine, up to 51% further power saving is achieved, and 421× speed up of parallel processing compared to the baseline, henceforth the efficiency is elevated over 43×. © 2025 IEEE.

关键词： Approximate Computing Compressive Sensing Convex Optimization Depth Reconstruction field-programmable gate array

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Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers

Enhancing Memory Capacity of Reservoir Computing with Delaye...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Hirayae, Soshi Yoshioka, Kanta Yokota, Atsuki Kawashima, Ichiro Tanaka, Yuichiro Katori, Yuichi Nomura, Osamu Morie, Takashi Tamukoh, Hakaru Kyushu Inst Technol Sch Engn Kitakyushu Fukuoka Japan Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka Japan Kyushu Inst Technol Res Ctr Neuromorph AI Hardware Kitakyushu Japan Future Univ Hakodate Sch Syst Informat Sci Hakodate Hokkaido Japan

ISBN: (纸本)9798350330991;9798350331004

To use reservoir computing (RC) for practical tasks, both a high memory capacity and nonlinearity are required;however, some RC models have the problem of a low memory capacity. We propose a delay mechanism for increasing the memory capacity in RC as well as a simple and small-scale digital circuit for implementing the delay mechanism. The proposed delay mechanism is integrated into the input layer of the RC model and is expected to be implemented in several RC models, such as material reservoirs and chaotic Boltzmann machine (CBM)-RC. We conducted experiments using a CBM-RC with a delay mechanism (CBM-RC-DL) and evaluated the performance improvement achieved by introducing a delay mechanism. We used CBM-RC as the base model because it is an appropriate model for the hardware implementation of large networks but has a low memory capacity. The experimental results for CBM-RC-DL indicated that the delay mechanism significantly increased the memory capacity of CBM-RC with the addition of a small-scale circuit. Furthermore, the entire synthesized CBM-RCDL was sufficiently small-scale to be implemented in a field-programmable gate array for edge computing, and it outperformed conventional methods in nonlinear autoregressive moving average 10 (NARMA10)-a benchmark task for time-series data processing. The proposed delay mechanism can facilitate the use of many RC models because of its simple structure.

关键词： neural networks reservoir computing field-programmable gate array memory capacity

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Degradation Observations of Protective Coatings: An Improved Version of Coating Impedance Detector

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IEEE ACCESS 2022年 10卷 18074-18080页

作者： Huan-Cheng Liao Zong-Han Cai Hung-Hsun Chen Cheng-Hsien Chung I-Chung Cheng Yueh-Lien Lee Natl Taiwan Univ Dept Engn Sci & Ocean Engn Taipei 10617 Taiwan Ship & Ocean Ind Res & Dev Ctr SOIC Taipei 100210 Taiwan Natl Taiwan Univ Dept Mech Engn Taipei 10617 Taiwan

This study proposes coating impedance detector 3.0 (CID 3.0), an improved version of our previously developed CID 2.0. The new circuit design in CID 3.0 has lower power consumption because it has fewer components, and it affords better accuracy through the modification of the analog part of CID 2.0 and the use of oversampling. This approach successfully afforded CID 3.0 with higher measurement stability for evaluating a high-performance coating with impedance values exceeding 10(9) Omega . Furthermore, CID 3.0 could detect impedance decreases associated with coating delamination when the coating suffers an attack.

关键词： Coatings Impedance Impedance measurement Monitoring Frequency measurement Corrosion Voltage measurement Coating degradation corrosion monitor field-programmable gate array oversampling electrochemical impedance spectroscopy

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A resource saving FPGA implementation approach to fractional Kalman filter

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IET CONTROL THEORY AND APPLICATIONS 2022年第13期16卷 1352-1363页

作者： Xu, Bo Bai, Libing Chen, Kai Tian, Lulu Univ Elect Sci & Technol China Sch Automat Engn Chengdu 611731 Peoples R China

The efficiency of the hardware implementations of fractional Kalman filter (FKF) heavily relies on the efficiency of realising the fractional-order derivative operator. In this paper, a generic software and hardware implementation of the FKF based on the Grunwald-Letnikov approximation is proposed and verified on a field-programmable gate array. The main advantage of this particular realisation is its resource saving capability on both software and hardware components (e.g. digital signal processing chips), and this enables fast and efficient real-time computation of the FKF. Furthermore, the performance of the FKF is evaluated via studying the mean square boundedness of the filtering error. At last, a mass-spring-damper example is implemented via Matlab simulations to verify the applicability of the proposed approach and moreover, a hardware experiment is also conducted to demonstrate the advantage of resource saving.

关键词： digital signal processing chips software components hardware experiment filtering error Grunwald-Letnikov approximation field-programmable gate array FKF generic software hardware implementation fractional-order derivative operator field programmable gate arrays fractional Kalman filter approximation theory particular realisation hardware-software codesign FPGA implementation approach mean square boundedness hardware components hardware implementations mass-spring-damper Matlab simulations Kalman filters

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Real-Time FPGA Investigation of Interplay Between Probabilistic Shaping and Forward Error Correction

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2022年第5期40卷 1339-1345页

作者： Zhang, Liangjun Tao, Kai Qian, Weifeng Wang, Weiming Liang, Junpeng Cai, Yi Feng, Zhenhua ZTE Corp State Key Lab Mobile Network & Mobile Multimedia Wuhan 430233 Peoples R China ZTE TX Inc Morristown NJ 07960 USA Soochow Univ Suzhou Jiangsu Peoples R China

In this work, we implement a complete probabilistic amplitude shaping (PAS) architecture on a field-programmable gate array (FPGA) platform to study the interplay between probabilistic shaping (PS) and forward error correction (FEC). Due to the fully parallelized input-output interfaces based on look up table (LUT) and low computational complexity without high-precision multiplication, hierarchical distribution matching (HiDM) is chosen as the solution for real time probabilistic shaping. In terms of FEC, we select two kinds of the mainstream soft decision-forward error correction (SD-FEC) algorithms currently used in optical communication system, namely Open FEC (OFEC) and soft-decision quasi-cyclic low-density parity-check (SD-QC-LDPC) codes. Through FPGA experimental investigation, we studied the impact of probabilistic shaping on OFEC and LDPC, respectively, based on PS-16QAM under moderate shaping, and also the impact of probabilistic shaping on LDPC code based on PS-64QAM under weak/strong shaping. The FPGA experimental results show that if pre-FEC bit error rate (BER) is used as the predictor, moderate shaping induces no degradation on the OFEC performance, while strong shaping slightly degrades the error correction performance of LDPC. Nevertheless, there is no error floor when the output BER is around 10(-15). However, if normalized generalized mutual information (NGMI) is selected as the predictor, the performance degradation of LDPC will become insignificant, which means pre-FEC BER may not a good predictor for LDPC in probabilistic shaping scenario. We also studied the impact of residual errors after FEC decoding on HiDM. The FPGA experimental results show that the increased BER after HiDM decoding is within 10 times compared to post-FEC BER.

关键词： field programmable gate arrays Parity check codes Forward error correction Real-time systems Probabilistic logic Table lookup Random access memory Distribution matching field-programmable gate array forward error correction optical fiber communication probabilistic shaping

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Model Predictive Control Strategy for Induction Motor Drive Using Lyapunov Stability Objective

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2022年第12期69卷 12119-12128页

作者： Gulbudak, Ozan Gokdag, Mustafa Komurcugil, Hasan Karabuk Univ Dept Elect Elect Engn TR-78050 Karabuk Turkey Eastern Mediterranean Univ Dept Comp Engn TR-99628 Famagusta Turkey

This article presents a novel Lyapunov-based model predictive control strategy for squirrel-cage induction motor fed by a voltage source inverter. The model predictive control method has received enormous attention thanks to its rapid response to load perturbations. However, the traditional model predictive control method may suffer from instability due to the poor choice of the objective function, weighting factors, or other design parameters. In particular, the selection of the objective function may not be sufficient to ensure global stability. Since the performance of the model predictive control method highly relies on the explicit model of the system, a simple penalization term in the objective function can lead to system instability. As a result, the transient and steady-state performances are negatively affected. The objective function is reformulated as the Lyapunov energy function to deal with this ambiguous situation in this article. The control input constraints are defined in the formulated optimal control problem, and the optimal solution is explored by assessing the Lyapunov stability criterion. The proposed method ensures asymptotic stability since the control action that satisfies the Lyapunov stability condition is selected. The experimental work proves the theoretical concepts. Moreover, the proposed method does not require the weighting factors to control the multiple control goals. The experimental results demonstrate that the proposed control strategy improves the steady-state performance. The machine torque and speed are well regulated, and the quality of the stator current is improved.

关键词： field-programmable gate array induction motor Lyapunov method model predictive control voltage-source inverter

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THx2 programmable Logic Block Architecture for Clockless Asynchronous FPGAs

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第7期69卷 2906-2915页

作者： Emmert, John M. Perumalla, Anvesh K. Hudson, Tristan J. Concha, Luis M. Univ Cincinnati Dept Elect Engn & Comp Sci Cincinnati OH 45221 USA

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our THx2 programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The THx2 threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the THx2 threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the THx2 threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the THx2 threshold cell-along with the symmetry of the mask- and field-programmable gate array logic cells-made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.

关键词： Computer architecture Logic gates Microprocessors field programmable gate arrays Trojan horses Layout Wires Assurance asynchronous field-programmable gate array mask-programmable gate array null convention logic programmable logic block security side-channel attacks split manufacturing threshold gates trust

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Gating function based on transmission delays and stochastic resonance in motif network with FPGA implementation

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NONLINEAR DYNAMICS 2022年第3期108卷 2731-2749页

作者： Hu, Zhicai Wang, Jiang Hao, Xinyu Li, Kai Tianjin Univ Sch Elect & Informat Engn Tianjin 30072 Peoples R China

Attuned function of different brain regions relies on the precise yet flexible communication between their subsystems, and flexible gating of information flow among brain motif network could increase neuronal response which is selected. However, the underlying mechanism remains to be investigated. In this paper, we present a hardware efficient, scalable, and real-time computing strategy for the implementation of large-scale motif cortical network via field-programmable gate array (FPGA). Based on FPGA network model, we explore the information transmission in cortical network by investigating the gating function from the perspective of stochastic resonance, which is an important way for neuronal population to communicate. Remarkably, it is found that the cortical network can only transmit signal when the excitatory-inhibitory (E/I) balance is lopsided, which is called as "E/I semi-balanced state." Moreover, time delay between populations affects the information transmission mainly by determining the phase timestamp at which the signal is transmitted from one region to another. In short, E/I semi-balance and time delay together realize the gating function to input in cortical motif network. The experimental results demonstrate that the gating function of information is determined by E/I semi-balance and time delay in cortical motif network. Besides, mean-field theory is applied to verify the simulation results, and the cortical network is found to resonate in the form of cycle dynamics. Verification result shows that the simulation speed on hardware is 27.4 ms, which is much better than the 90 s on MATLAB. Consequently, the hardware synthesis results indicate high computational speed and low area utilization, which helps to deploy the function realization of biological neuronal network in intelligent control and remote communication.

关键词： Stochastic resonance Gating function field-programmable gate array Information transmission

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