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Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis

WIRELESS PERSONAL COMMUNICATIONS 2022年第3期127卷 1869-1878页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 field programmable gate array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from Math-Works. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. MATLAB HDL coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in MATLAB. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications.

关键词： Hardware description language Register transfer language field-programmable gate array High-level synthesis DSP filter Vivado MATLAB HDL coder

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Very large scale integration implementation of seizure detection system with on-chip support vector machine classifier

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IET CIRCUITS DEVICES & SYSTEMS 2022年第1期16卷 1-12页

作者： Shanmugam, Shalini Dharmar, Selvathi Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi Tamil Nadu India

Epilepsy is one of the most common neurological disorders;it affects millions of people globally. Because of the risks to health that it causes, the study and analysis of epilepsy have been given considerable attention in the biomedical field. In a neurological diagnosis, an automated device for detecting seizures or epilepsy from an electroencephalogram (EEG) signal has a significant role. This research work proposes a very large scale integration implementation system for the automatic detection of seizures. Before classification, feature extraction was performed by discrete wavelet transform (DWT) and on-chip classification was performed by a linear support vector machine. The polyphase architecture of Daubechies fourth-order wavelet three-level DWT was used to minimize computational time. The systolic array architecture-based support vector machine classifier using parallel processing helps to minimize the computational complexity of the proposed method. This research work uses an open access EEG dataset. Hardware implementation was done on a field-programmable gate array (FPGA). Efficient results were produced compared with the existing system on chip (SoC) and FPGA seizure detection systems.

关键词： on-chip classification medical signal processing neurophysiology epilepsy systolic arrays scale integration implementation system feature extraction automatic detection polyphase architecture hardware implementation signal classification medical disorders computational time common neurological disorders biomedical field linear support vector machine field-programmable gate array on-chip support vector machine classifier seizure detection system electroencephalogram signal neurological diagnosis medical signal detection support vector machines automated device field programmable gate arrays systolic array architecture-based support vector machine classifier Daubechies fourth-order wavelet three-level DWT electroencephalography wavelet transforms discrete wavelet transforms

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Efficient Reconfigurable Mixed Precision l1 Solver for Compressive Depth Reconstruction

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2022年第10期94卷 1083-1099页

作者： Wu, Yun Wallace, Andrew M. Mota, Joao F. C. Assmann, Andreas Stewart, Brian Heriot Watt Univ Sch Engn & Phys Sci Edinburgh EH14 4AS Midlothian Scotland STMicroelect R&D Ltd Imaging Div Edinburgh EH3 5DA Midlothian Scotland

Rapid reconstruction of depth images from sparsely sampled data is important for many applications in machine perception, including robot or vehicle assistance or autonomy. Approximate computing techniques have been widely adopted to reduce resource consumption and increase efficiency in energy and resource constrained systems, especially targeted at FPGA and solid state implementation. Whereas previous work has focused on approximate, but static, representation of data in LiDAR systems, in this paper we show how the flexibility of an arbitrary precision accelerator with fine-grain tuning allows a better trade-off between algorithmic performance and implementation efficiency. A mixed precision framework of l(1) solvers is presented, with compact ADMM and PGD, for the lasso problem, enabling compressive depth reconstruction by varying the precision scaling in single bit granularity during the iterative optimization process. Implementing mixed precision l(1) solvers on an FPGA with a pipelined architecture for depth image reconstruction across various sensing scenarios, over 74% savings in hardware resources and 60% in power are achieved with only minor reductions in reconstructed depth image quality when compared to single float precision, while over 10% saving in hardware resources and power is achieved compared to relative consistently reduced precision solutions.

关键词： Compressive sensing Depth reconstruction Mixed precision Alternating direction method of multipliers Proximal gradient descent field-programmable gate array

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A Novel Integrated Cochlear Model based on Ergodic Sequential Logic Dynamics: Reproduction of Mammalian Nonlinear Sound Processing and Efficient FPGA Implementation 56

A Novel Integrated Cochlear Model based on Ergodic Sequentia...

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56th IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Kishimoto, Yui Kubota, Itsuki Torikai, Hiroyuki Hosei Univ Grad Sch Sci & Engn Tokyo Japan

ISBN: (纸本)9781665451093

In this paper, a novel hardware-efficient integrated cochlear model, whose nonlinear dynamics is described by ergodic sequential logics, is presented. It is shown that the presented cochlear model can reproduce combination tone generation of a mammalian cochlea, which is one of the most typical nonlinear sound processing functions. In addition, the presented model is implemented by a field-programmable gate array (FPGA) and its operations are verified by experiments. It is then shown that the presented model consumes much less hardware resources and much less power compared to a standard ordinary differential equation (ODE) model of cochlea.

关键词： Electronic cochlear model Nonlinear sound processing field-programmable gate array Cochlear Implant

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Data Acquisition and Processing Module with a Network Interface for MWPC Detectors with Delay-Line Readout

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JOURNAL OF SURFACE INVESTIGATION 2022年第6期16卷 1023-1028页

作者： Golubev, M. A. Saveleva, T., V Gapon, O. N. Kolkhidashvili, M. R. Polyushkin, A. O. Solovei, V. A. Natl Res Ctr Kurchatov Inst Konstantinov Petersburg Nucl Phys Inst Gatchina 188300 Russia

A prototype of a data acquisition and processing module with a network interface for two-dimensional multiwire proportional chamber detectors with delay-line readout is developed and tested. The device consists of a domestically produced printed circuit board with inputs including a neutron-beam chopper, a neutron-beam monitor and a spin flipper. The board contains a four-channel time-to-code converter, which digitizes the delays between pulses, and a single-board computer with a processor combined with a programmable logic integrated circuit. For this single-board computer, original software is developed that collects and transmits the raw data of the experiment in digital form (coordinates, neutron time-of-flight count, etc.) though the network to the client, and the user interface of the future detector. For data collection, the web server and web client used the firmware language, Verilog programmable logic integrated circuit, programming languages C and JavaScript, respectively. In the future, the tested scheme, implemented in a more compact form, will become an integral part of neutron detectors along with a multi-wire proportional chamber with two-coordinate delay lines and a five-channel analog-signal processing unit. Work with the module, and with the neutron detector in the future, is carried out through a local network in a web browser or an alternative client. The web client for a web browser enables the accumulation of statistics and the viewing of a 2D image from the detector during the experiment, it is also possible to navigate through 2D images of individual time channels for time-of-flight experiments and save all data in the common CSV text format, viewable in office spreadsheets.

关键词： multi-wire proportional chamber delay line field-programmable gate array neutron detector differential non-linearity web interface local area network data processing software hardware data transfer

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Dual-Hysteresis Band Control of Nine-Switch Inverter to Control Two Induction Motors

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IEEE TRANSACTIONS ON ENERGY CONVERSION 2022年第2期37卷 788-799页

作者： Gulbudak, Ozan Gokdag, Mustafa Karabuk Univ Elect Elect Engn TR-78050 Karabuk Turkey

This paper presents a dual-hysteresis band control method for multi-drive systems based on a nine-switch inverter. The drive system contains two independent three-phase induction motors fed by a nine-switch inverter. Independent control of torque, speed, and stator current of two load stages is achieved. The proposed strategy offers a reliable control operation of both induction machines under individual load profiles. Instead of using independent sets of three-phase voltage source converters, the nine-switch inverter is used to drive separate machines. Thus, the volume and size of the power stage are noticeably reduced due to the use of fewer semiconductors. The theoretical concept and design steps of the proposed method are presented. The performance of the closed-loop independent motor control scheme is experimentally validated using a 3.2 kW lab-scaled nine-switch inverter prototype and Altera Cyclone IV field-programmable gate array.

关键词： Inverters Switches Induction motors Control systems Voltage control Rotors Torque Nine-switch inverter multi-drive systems multi-machines control hysteresis current control variable-speed drives field-programmable gate array

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Design and Synchronization of Chaos-Based True Random Number Generators and Its FPGA Implementation

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IEEE ACCESS 2022年 10卷 8279-8286页

作者： Liao, T. L. Wan, P. Y. Yan, Jun-Juh Natl Cheng Kung Univ Dept Engn Sci Tainan 701 Taiwan Natl Chin Yi Univ Technol Dept Elect Engn Taichung 41107 Taiwan

In this paper, a new chaos-based true random number generator (TRNG) and a sliding mode controller (SMC) to synchronize the proposed TRNGs are proposed. Firstly, the continuous chaotic system is transformed into a discrete system that preserves the original continuous system's chaotic behavior and makes it easy to realize with the field-programmable gate array (FPGA) for synchronization control. Then, a discrete SMC is introduced to solve the synchronization problem of the master-slave discrete chaotic systems. Subsequently, a novel hybrid function integrated with the El-Gamal algorithm is proposed to complete the TRNG design. Finally, the FPGA-based realization of the synchronized master-slave TRNGs is implemented. The randomness quality of the proposed TRNGs has been ensured by using Shannon's entropy and histogram analysis. Furthermore, the National Institute of Standards and Technology (NIST) test suite has also been introduced to evaluate the proposed TRNGs and compare with the existing results in the literature.

关键词： Synchronization Generators field programmable gate arrays Chaotic communication Main-secondary Heuristic algorithms Signal processing algorithms True random number generators chaotic systems synchronization sliding mode control field-programmable gate array

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Hardware Implementation of MQTT Broker and Precise Time Synchronization Using IoT Devices

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IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING 2022年第2期17卷 209-217页

作者： Yamamoto, Koutarou Fukuhara, Akihiro Nishi, Hiroaki Keio Univ Grad Sch Sci & Technol Kohoku Ku 3-14-1Hiyoshi Yokohama Kanagawa 2238522 Japan Keio Univ Dept Syst Design Fac Sci & Technol Kohoku Ku 3-14-1Hiyoshi Yokohama Kanagawa 2238522 Japan

In recent years, while internet of things (IoT) devices and cloud computing environments have been penetrated, the increase in communication latency and concentration of traffic caused by data centers has deteriorated the quality of some network services. Message Queuing Telemetry Transport (MQTT) is a well-known protocol for exchanging messages between dedicated applications. MQTT employs a publish-subscribe model in which a broker mediates communication between IoT devices and applications. To improve service quality, the processing latency of the broker should be reduced. Moreover, the broker's throughput must be increased. IoT devices, in particular, must maintain a highly accurate time to provide some IoT services. This study proposed hardware implementation of MQTT broker and evaluated the accuracy of an MQTT-based time synchronization method. The proposed MQTT architecture's hardware resource utilization is also provided. We confirmed that our implementation achieved high throughput, low latency, and low jitter MQTT broker, which satisfies the smart city services for automated drive and power control, which must be less than a few milliseconds. (c) 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

关键词： field-programmable gate array MQTT edge computing internet of things time synchronization

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Traffic Flow Optimization using a Chaotic Boltzmann Machine Annealer on an FPGA 22

Traffic Flow Optimization using a Chaotic Boltzmann Machine ...

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22nd International Conference on field programmable Technology (ICFPT)

作者： Yoshioka, Kanta Tanaka, Yuichiro Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka Japan Kyushu Inst Technol Res Ctr Neuromorph AI Hardware Kitakyushu Fukuoka Japan

ISBN: (纸本)9798350359114

We demonstrate a chaotic Boltzmann machine annealer, which is a field-programmable gate array (FPGA)-based high-performance annealing machine, and a control system powered by two open-source software packages. The annealer is employed in solving a large-scale real-world optimization problem, the traffic flow optimization. This involves distributing 500 car routes between the Haneda Airport area to the Pacifico Yokohama area, the venue of the International Conference on field programmable Technology 2023, while minimizing the total driving distance and preventing traffic jams. We obtain solutions that are comparable in accuracy to solutions of simulated annealing running on a graphics processing unit (GPU-SA) and a central processing unit (CPU-SA). The annealing machine on an FPGA is approximately 571 and 97600 times as fast as the GPUSA and the CPU-SA, respectively. We will demonstrate solving traffic flow optimization in the towns familiar to the visitors.

关键词： neural networks Ising machine annealing machine field-programmable gate array

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A real-time FPGA accelerated stream processing for hyperspectral image classification

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GEOCARTO INTERNATIONAL 2022年第1期37卷 52-69页

作者： Gyaneshwar, Dubacharla Nidamanuri, Rama Rao Indian Inst Space Sci & Technol Remote Sensing Lab Dept Earth & Space Sci Thiruvananthapuram 695547 Kerala India

Realizing real-time classification of hyperspectral imagery has attracted researchers across various scientific and engineering disciplines. Several time-critical applications of high-resolution hyperspectral imaging require analysis of hyperspectral imagery with minimal turnaround time. In this regard, field-programmable gate arrays (FPGAs) provide cost-effective performance over the other high-performance reconfigurable computing systems. Developing such efficient systems poses several technical challenges such as designing and validating the FPGA architecture. A rapid prototyping approach offers several benefits in designing and developing FPGA architectures. This paper proposes a rapid prototyping method for the design and implementation of a multi-class support vector machine (MSVM) algorithm for real-time hyperspectral imagery classification using a low-cost FPGA system. We have evaluated design performance in terms of overall accuracy, resource utilization as well as timing requirements using four different datasets containing airborne, drone, and ground-based hyperspectral imagery. Experimental results show that the proposed FPGA design performs classification under strict real-time constraints.

关键词： Hyperspectral imagery real-time processing field-programmable gate array rapid prototyping multi-class support vector machine

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