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A High-Performance and Scalable Hardware Architecture for Isogeny-Based Cryptography

IEEE TRANSACTIONS ON COMPUTERS 2018年第11期67卷 1594-1609页

作者： Koziel, Brian Azarderakhsh, Reza Kermani, Mehran Mozaffari Texas Instruments Inc Dallas TX 75243 USA Florida Atlantic Univ Comp & Elect Engn & Comp Sci Dept Boca Raton FL 33431 USA Florida Atlantic Univ I SENSE Boca Raton FL 33431 USA Univ S Florida Comp Sci & Engn Dept Tampa FL 33620 USA

In this work, we present a high-performance and scalable architecture for isogeny-based cryptosystems. In particular, we use the architecture in a fast, constant-time FPGA implementation of the quantum-resistant supersingular isogeny Diffie-Hellman (SIDH) key exchange protocol. On a Virtex-7 FPGA, we show that our architecture is scalable by implementing at 83, 124, 168, and 252-bit quantum security levels. This is the first SIDH implementation at close to the 256-bit quantum security level to appear in literature. Further, our implementation completes the SIDH protocol 2 times faster than performance-optimized software implementations and 1.34 times faster than the previous best FPGA implementation, both running a similar set of formulas. Our implementation employs inversion-free projective isogeny formulas. By replicating multipliers and utilizing an efficient scheduling methodology, we can heavily parallelize quadratic extension field arithmetic and the isogeny evaluation stage of the large-degree isogeny computation. For a constant-time implementation of 124-bit quantum security SIDH on a Virtex-7 FPGA, we generate ephemeral public keys in 8.0 and 8.6 ms and generate the shared secret key in 7.1 and 7.9 ms for Alice and Bob, respectively. Finally, we show that this architecture could also be used to efficiently generate undeniable and digital signatures based on supersingular isogenies.

关键词： Elliptic curve cryptography field-programmable gate array isogeny-based cryptography post quantum cryptography

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ON-State Reliability of Cu Atom Switch Under Current-Temperature Stress

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2015年第9期62卷 2992-2997页

作者： Tada, Munehiro Okamoto, Koichiro Sakamoto, Toshitsugu Hada, Hiromitsu NEC Corp Ltd Tsukuba Ibaraki 3058501 Japan

The dc current-stress tolerance of the ON-state Cu atom switch is evaluated at elevated temperature. It is revealed that the reset-direction current stress causes time-dependent failures, which originate from the E-field-driven diffusion of Cu in the conducting bridge. A new empirical lifetime estimation model, including the Joule heating effect, gives an allowable maximum current per atom switch of I-max = 115 mu A, which is large enough to satisfy the requirements for signal routing under currents that are average (18 mu A) and peak (63 mu A) in the reconfigurable switch block operated at 500 MHz at 125 degrees C.

关键词： Atom switch field-programmable gate array nonvolatile memory programmable logic device polymer reconfigurable logic solid electrolyte

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Algorithms for an FPGA switch module routing problem with application to global routing

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1997年第1期16卷 32-46页

作者： Thakur, S Chang, YW Wong, DF Muthukrishnan, S NATL CHIAO TUNG UNIV DEPT COMP & INFORMAT SCI HSINCHU 300 TAIWAN UNIV TEXAS DEPT COMP SCI AUSTIN TX 78712 USA LUCENT TECHNOL MURRAY HILL NJ 07974 USA

We consider a switch module routing problem for symmetrical-array field-programmable gate arrays (FPGA's). This problem was first introduced in [21], They used it to evaluate the routability properties of switch modules which they proposed, Only an approximation algorithm for the problem was proposed by them, We give an optimal algorithm for the problem based on integer linear programming (ILP), Experiments show that this formulation leads to fast and efficient solutions to practical-sized problems, We then propose a precomputation that eliminates the need to use ILP era-line, We also identify special cases of this problem that reduce to problems for whom efficient algorithms are known, Thus, the switch module routing problem can be solved in polynomial time for these special cases, Using our solution to the switch module routing problem, we propose a new metric to estimate the congestion in each switch module in the FPGA. We demonstrate the use of this metric in a global router, A comparison with a global router guided by the density of the routing channels shows that our metric leads to far superior global and detailed routing solutions.

关键词： field-programmable gate array global routing

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FPGA-Based Implementation of Real-Time Cardiologist-Level Arrhythmia Detection and Classification in Electrocardiograms Using Novel Deep Learning

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2024年第0期

作者： Chandrasekaran, Saravanakumar Chandran, Srinivasan Selvam, Immaculate Joy SRM Valliammai Engn Coll ECE Chennai Tamil Nadu India Rajalakshmi Engn Coll EEE Chennai Tamil Nadu India Saveetha Engn Coll ECE Chennai Tamil Nadu India

Cardiac arrhythmia refers to irregular heartbeats caused by anomalies in electrical transmission in the heart muscle, and it is an important threat to cardiovascular health. Conventional monitoring and diagnosis still depend on the laborious visual examination of electrocardiogram (ECG) devices, even though ECG signals are dynamic and complex. This paper discusses the need for an automated system to assist clinicians in efficiently recognizing arrhythmias. The existing machine-learning (ML) algorithms have extensive training cycles and require manual feature selection;to eliminate this, we present a novel deep learning (DL) architecture. Our research introduces a novel approach to ECG classification by combining the vision transformer (ViT) and the capsule network (CapsNet) into a hybrid model named ViT-Cap. We conduct necessary preprocessing operations, including noise removal and signal-to-image conversion using short-time Fourier transform (SIFT) and continuous wavelet transform (CWT) algorithms, on both normal and abnormal ECG data obtained from the MIT-BIH database. The proposed model intelligently focuses on crucial features by leveraging global and local attention to explore spectrogram and scalogram image data. Initially, the model divides the images into smaller patches and linearly embeds each patch. Features are then extracted using a transformer encoder, followed by classification using the capsule module with feature vectors from the ViT module. Comparisons with existing conventional models show that our proposed model outperforms the original ViT and CapsNet in terms of classification accuracy for both binary and multi-class ECG classification. The experimental findings demonstrate an accuracy of 99% on both scalogram and spectrogram images. Comparative analysis with state-of-the-art methodologies confirms the superiority of our framework. Additionally, we configure a field-programmable gate array (FPGA) to implement the proposed model for real-time ar

关键词： accuracy arrhythmia capsule network deep learning electrocardiogram field-programmable gate array power processing time vision transformer

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An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2020年第3期28卷 1656-1672页

作者： Ben Atitallah, Ahmed Kammoun, Manel Ben Atitallah, Rabie Jouf Univ Dept Elect Engn Aljouf Saudi Arabia Univ Sfax LETI ENIS Sfax Tunisia Galatasaray Univ Dept Comp Sci Istanbul Turkey

This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 x 4, 8 x 8, 16 x 16, and 32 x 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standard-cells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) environment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

关键词： High-efficiency video coding decoder IDCT inverse quantization software/hardware environment field-programmable gate array

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Degradation Observations of Protective Coatings: An Improved Version of Coating Impedance Detector

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IEEE ACCESS 2022年 10卷 18074-18080页

作者： Huan-Cheng Liao Zong-Han Cai Hung-Hsun Chen Cheng-Hsien Chung I-Chung Cheng Yueh-Lien Lee Natl Taiwan Univ Dept Engn Sci & Ocean Engn Taipei 10617 Taiwan Ship & Ocean Ind Res & Dev Ctr SOIC Taipei 100210 Taiwan Natl Taiwan Univ Dept Mech Engn Taipei 10617 Taiwan

This study proposes coating impedance detector 3.0 (CID 3.0), an improved version of our previously developed CID 2.0. The new circuit design in CID 3.0 has lower power consumption because it has fewer components, and it affords better accuracy through the modification of the analog part of CID 2.0 and the use of oversampling. This approach successfully afforded CID 3.0 with higher measurement stability for evaluating a high-performance coating with impedance values exceeding 10(9) Omega . Furthermore, CID 3.0 could detect impedance decreases associated with coating delamination when the coating suffers an attack.

关键词： Coatings Impedance Impedance measurement Monitoring Frequency measurement Corrosion Voltage measurement Coating degradation corrosion monitor field-programmable gate array oversampling electrochemical impedance spectroscopy

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Converter Topology for Megawatt Scale Applications With Reduced Filtering Requirements, Formed of IGBT Bridge Operating in the 1000 Hz Region With Parallel Part-Rated High-Frequency SiC MOSFET Bridge

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2024年第1期39卷 799-813页

作者： Li, Ning Macavilca, Marlee Basurto Wu, Chenqi Finney, Stephen Judge, Paul D. Univ Edinburgh Sch Engn Inst Energy Syst Edinburgh EH9 3JL Midlothian Scotland

This article investigates the design and control of the parallel-hybrid converter (PHC), which consists of parallel connection of a silicon insulated gate bipolar transistor (IGBT) bridge and a partially rated silicon carbide (SiC) MOSFETs bridge with a shared dc bus. The IGBT bridge processes the bulk of the power, while switching at a low frequency to maximize efficiency, while the SiC MOSFETs bridge's lower relative switching loss is exploited to filter low-order harmonics from the IGBT bridge. A finite-set model predictive controller is detailed that allows IGBT switching frequencies down to 1 kHz to be achieved while also tightly controlling the magnitude of current in the SiC bridge. A genetic algorithm is utilized to automatically tune the control and investigate the design of the output filter as well as the influence of the controller time-step and horizon length on the performance. Power loss estimates of a 1.5MWapplication case are made showing potential for significant power-loss reductions. Experimental tests validate an field-programmable gate array (FPGA) implementation of the controller and topologies performance, with IGBT bridge frequencies below 1.2 kHz and grid-current total harmonic distortion below 3% achieved. The ability of converter to switch operation between a high-current and a low-current mode and dynamic performance is also verified.

关键词： Active filtering depth-first search (DFS) field-programmable gate array model predictive control partial load efficiency power electronic converter silicon carbide (SiC) MOSFETs

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Electronic Interpolation Interface Based on Linear Subdivision Method for Sinusoidal Optical Encoders

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IEEE SENSORS JOURNAL 2020年第7期20卷 3646-3654页

作者： Zhao, Guobo Ye, Guoyong Liu, Hui Lei, Biao Li, Xuan Han, Weiliang Liu, Hongzhong Xi An Jiao Tong Univ State Key Lab Mfg Syst Engn Xian 710049 Peoples R China

Sinusoidal optical encoders are widely utilized in precision positioning systems. With the development of precision positioning systems, higher resolution is required. Electronic interpolation is a promising technique to further improve the resolution of sinusoidal optical encoders. In this paper, we propose an electronic interpolation interface based on linear subdivision method with better practical accuracy. Firstly, a pseudo-linearized signal based on the difference between the absolute values of sine and cosine signals is generated. Then, a compensation signal with a ratiometric form is constructed, which has a better robustness to the non-ideal input signals. Finally, a nearly perfect linear output signal is obtained by combining these two signals. Thus, the displacement can be linearly determined without LUTs. It is shown that the theoretical nonlinear error of the proposed method is below 0.08 degrees over a signal period of 360 degrees, which corresponds to a theoretical interpolation error of 0.018 mu m for sinusoidal optical encoders with a pitch of 80 mu m. Moreover, theoretical analysis and simulation results indicate that the proposed method offers a better practical accuracy. In the experiment, the proposed electronic interpolation interface is developed in a field-programmable gate array (FPGA), and experiments are carried out to evaluate its performance. Both the theoretical and experiment results verify its effectiveness.

关键词： Sinusoidal optical encoder linearization technique electronic interpolation precision phase solution field-programmable gate array

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High-Speed and Adaptive FPGA-Based Privacy Amplification in Quantum Key Distribution

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IEEE ACCESS 2019年 7卷 21482-21490页

作者： Li, Qiong Yan, Bing-Ze Mao, Hao-Kun Xue, Xiao-Feng Han, Qi Guo, Hong Harbin Inst Technol Sch Comp Sci & Technol Informat Countermeasure Tech Inst Harbin 150001 Heilongjiang Peoples R China Peking Univ Sch Elect Engn & Comp Sci State Key Lab Adv Opt Commun Syst & Networks Ctr Computat Sci & EngnCtr Quantum Informat Tech Beijing 100871 Peoples R China

Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to shrink the eavesdropper's information about the final key almost to zero. With the increase of repeat frequency of discrete variable QKD (DV-QKD) system, PA processing speed has become the bottleneck in many highspeed DV-QKD systems. In this paper, a high-speed adaptive field-programmable gate array (FPGA)-based PA scheme using a fast Fourier transform (FFT) is presented. To decrease the computation complexity, a modified 2-D FFT-based Toeplitz PA scheme is designed. To increase the processing speed of the scheme on the constraint of limited resources, a real-value oriented FFT acceleration method and a fast read/write balanced matrix transposition method are designed and implemented in our scheme. The experimental results on a Xilinx Virtex-6 FPGA demonstrate that the throughput is nearly double of the latest FPGA based Toeplitz PA scheme according to the literature. Besides, this scheme owns not only the good adaptivity to compression ratio but also the compression ratio independent resource consumption. Therefore, this scheme can fit many high-speed QKD applications.

关键词： Quantum key distribution privacy amplification fast Fourier transform field-programmable gate array

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Event management for large scale event-driven digital hardware spiking neural networks

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NEURAL NETWORKS 2013年 45卷 83-93页

作者： Caron, Louis-Charles D'Haene, Michiel Mailhot, Frederic Schrauwen, Benjamin Rouat, Jean Univ Sherbrooke NECOTIS Sherbrooke PQ J1K 2R1 Canada Univ Ghent Reservoir Lab B-9000 Ghent Belgium

The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65 536 neurons and 513 184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406 x 158 pixel image is segmented in 200 ms. (C) 2013 Elsevier Ltd. All rights reserved.

关键词： Neuromorphic engineering field-programmable gate array Pipelined heap queue Event-driven simulation Spiking neural network

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