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IEEE 2nd German Education Conference (GECon)

作者： Al Amin, Rashed Wiese, Veit Rahman, Mohammad Musfiqur Jacobs, Sven Jaschke, Steffen Obermaisser, Roman Univ Siegen Inst Embedded Syst Siegen Germany Univ Siegen Comp Sci Educ Siegen Germany

ISBN: (纸本)9798350348132

Reconfigurable System-on-Chip (SoC) is a computing architecture that allows users to program and reprogram the hardware to perform different tasks, making it highly flexible and adaptable. Due to its potential to significantly accelerate various applications, reconfigurable SoC has become a subject of much research for academicians and industry. On the other hand, the classical practice of experimenting in the laboratory has been changing radically with the advanced utilization of computers, electronic devices, and the internet. As a result, it has given birth to a new concept of laboratory practice called Internet-of-Things (IoT) based collaborative simulation laboratory, which enables students to access and use the laboratory equipment at their convenience, enabling them to learn at their own pace and comfort. First, this paper reviewed the state of the art of reconfigurable SoC, specially field-programmable gate arrays (FPGAs) laboratory architecture. Then, it developed an IoT-based collaborative simulation laboratory for reconfigurable SoC, allowing multiple students to work together to solve laboratory tasks remotely. Furthermore, this laboratory architecture is for reconfigurable FPGAs, which can manage several tasks automatically, such as logic synthesis, logic simulation, and FPGA run from multiple FPGAs or SoC. In addition to its benefits, the capability to virtualize user input/output interfaces and remotely measure the design's response further enhances its advantages. However, this proposed laboratory architecture is essential not only for doing laboratory tasks remotely but also simplifies the existing teaching methods and helping evaluate student performance in the examination.

关键词： system-on-chip field-programmable gate array internet-of-things remote laboratory

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High-Level Synthesis versus Hardware Construction

High-Level Synthesis versus Hardware Construction

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Kamkin, Alexander Chupilko, Mikhail Lebedev, Mikhail Smolov, Sergey Gaydadjiev, Georgi RAS ISP Moscow Russia Plekhanov RUE Moscow Russia HSE MSU MIPT Moscow Russia Univ Groningen Groningen Netherlands

ISBN: (纸本)9798350396249

Application-specific systems with FPGA accelerators are often designed using high-level synthesis or hardware construction tools. Nowadays, there are many frameworks available, both open-source and commercial. In this work, we aim at a fair comparison of several languages (and tools), including Verilog (our baseline), Chisel, Bluespec SystemVerilog (Bluespec Compiler), DSLX (XLS), MaxJ (MaxCompiler), and C (Bambu and Vivado HLS). Our analysis has been carried out using a representative example of 8x8 inverse discrete cosine transform (IDCT), a widely used algorithm engaged in JPEG and MPEG decoders. The metrics under consideration include: (a) the degree of automation (how much less code is required compared to Verilog), (b) the controllability (possibility to achieve given design characteristics, namely a given ratio of the performance and area), and (c) the flexibility (ease of design modifications to achieve certain characteristics). Rather than focusing on computational kernels only, we use AXI-Stream wrappers for the synthesized implementations, which allows adequately evaluating characteristics of the designs when they are used as parts of real systems. Our study shows clear examples of what impact specific optimizations (tool settings and source code modifications) have on the overall system performance and area. It emphasizes how important is to be able to control the balance between the communication interface utilization and the computational kernel performance and delivers clear guidelines for the next generation tools for designing FPGA-accelerator-based systems.

关键词： electronic design automation application-specific computing hardware construction high-level synthesis field-programmable gate array inverse discrete cosine transform

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PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference 22

PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latenc...

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22nd International Conference on field programmable Technology (ICFPT)

作者： Andronic, Marta Constantinides, George A. Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (纸本)9798350359114

field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has hardcoded the combination of linear maps and nonlinear activations inside FPGA lookup tables (LUTs). Our work is motivated by the idea that the LUTs in an FPGA can be used to implement a much greater variety of functions than this. In this paper, we propose a novel approach to training neural networks for FPGA deployment using multivariate polynomials as the basic building block. Our method takes advantage of the flexibility offered by the soft logic, hiding the polynomial evaluation inside the LUTs with minimal overhead. We show that by using polynomial building blocks, we can achieve the same accuracy using considerably fewer layers of soft logic than by using linear functions, leading to significant latency and area improvements. We demonstrate the effectiveness of this approach in three tasks: network intrusion detection, jet identification at the CERN Large Hadron Collider, and handwritten digit recognition using the MNIST dataset.

关键词： deep learning inference field-programmable gate array hardware accelerator LUT-based neural networks soft logic

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FPGA-Accelerated Password Cracking

FPGA-Accelerated Password Cracking

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2023 Congress in Computer Science, Computer Engineering, and Applied Computing, CSCE 2023

作者： Britten, Eric Gofman, Mikhail Bai, Yu California State University Fullerton Department of Computer Science Fullerton United States California State University Fullerton Department of Electrical and Computer Engineering Fullerton United States

ISBN: (纸本)9798350327595

Passwords are a common way of securing systems and applications from unauthorized access. However, passwords can be vulnerable to attackers who try to crack them by using random guesses, common patterns (e.g., password topologies), dictionary words, or leaked passwords. In this paper, we propose a hardware-accelerated password cracking method that leverages field-programmable gate array (FPGA) technology to recover passwords hashed with the sha512crypt algorithm. This algorithm is widely used on Linux systems. Our approach focuses on fast development to simulate a casual attacker who wants to boost their password cracking performance by using the speed and parallelism of FPGAs, which can outperform traditional CPUs and GPUs. Using C++ high-level language (a technique called high-level synthesis), we created a hardware device (i.e., a core) that runs the sha512crypt algorithm on the Zynq Z-7020 CPU-FPGA hybrid chip. We then tested the password cracking speed of our core (passwords/sec) and compared it to the AMD Ryzen 9 and Apple M1 Max CPUs. Based on the results of one core and two parallel sha512crypt cores on our chip, the maximum that could fit, we estimated that an FPGA chip with more than 8 sha512crypt cores and the same parameters as our chip could crack 10-character passwords at 360 passwords/sec, which is faster than a single-threaded sha512crypt on either CPU. We also projected that with 15 cores, we could achieve a speed of 675 passwords/sec, which is twice as fast as either of the CPUs. We think this work is a useful addition to the research on cybersecurity applications of FPGAs, as few works have tried to break sha512crypt on the FPGA. In the future, we will implement our design on modern FPGA chips that can accommodate more than 10 cores, optimize our designs and evaluation methodology, and perform a more extensive evaluation. © 2023 IEEE.

关键词： cybersecurity field-programmable gate array FPGA password cracking passwords Security

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Optimal Selection of Switch Model Parameters for ADC-Based Full-Bridge Converter

Optimal Selection of Switch Model Parameters for ADC-Based F...

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2023 IEEE International Conference on Electrical, Computer and Energy Technologies, ICECET 2023

作者： Alsarayreh, Saif Süto, Zoltán University of Technology and Economics Department of Automation and Applied Informatics Budapest Budapest Hungary

ISBN: (纸本)9798350327816

The incorporation of real-time Hardware-In-the-Loop (HIL) simulators has become one of the pillars of the power electronics control design cycle. This integration is necessary to verify the effectiveness of controller implementations. Despite the rapid evolution in FPGA devices' computational capacity employed by Hardware-in-the-Loop (HIL) tools, developers are consistently faced with the need to strike a balance between acceptable accuracy and the practicality of implementing models and techniques. The methodology presented in this paper is for implementing a full-bridge converter using the Associate Discrete Circuit (ADC) model, specifically designed for real-time simulator applications. Furthermore, this study presents a novel methodology for parameter selection of (ADC) parameters utilizing the Artificial Bee Colony algorithm (ABC). The utilization of the ADC-based model facilitates the establishment of a uniform converter topology during simulation, irrespective of the switch states. The simulation results demonstrate the effectiveness of the introduced methodology in selecting optimal parameters for an ADC switch-based full-bridge converter, reducing overshoot in the converter's output voltage and current. © 2023 IEEE.

关键词： Artificial bee colony field-programmable gate array Full-bridge converter Optimization algorithm Real-time Simulation Terms-Associate Discrete Circuit

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FPGA-Embedded Anomaly Detection System for Milling Process

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IEEE ACCESS 2021年 9卷 124059-124069页

作者： Zabinski, Tomasz Hajduk, Zbigniew Kluska, Jacek Gniewek, Leslaw Rzeszow Univ Technol Dept Elect & Comp Engn PL-35959 Rzeszow Poland

The main goal of this work is to design a supervising controller able to detect an anomaly in the milling process and implement the soultion in field programmable gate array (FPGA) chip. Executing this task, the controller continuously monitors the vibration signal coming from the acceleration sensor, installed on the milling machine, and striving to isolate new vibration patterns which are different from typical patterns recorded for the correct milling process. The detection method relies on determining selected signal features in the frequency domain and applying an auto-associative neural network (AANN) for novelty detection. It has been shown that by exercising the frequency spectrum of the vibration signal, extracting specific features of the signal's spectrum, and using an auto-associative neural network, it is possible to detect anomalies in a milling process with relatively high efficiency. The accuracy, sensitivity, specificity, precision, and false alarm rate are equal to 94.3, 100, 91.2, 88.9, and 8.8 percent. All necessary calculations can be accomplished by the developed single-chip FPGA embedded supervising controller. The controller allows high-speed calculations under low power consumption. It characterizes high reliability and low price compared to typically encountered solutions.

关键词： Milling Anomaly detection field programmable gate arrays Tools Vibrations Feature extraction Real-time systems Anomaly detection autoencoder field-programmable gate array vibration analysis

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A Soft Computing Approach to Crack Detection and Impact Source Identification with field-programmable gate array Implementation

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ADVANCES IN FUZZY SYSTEMS 2013年第unknown期2013卷

作者： Dixit, Arati M. Singh, Harpreet Def Inst Adv Technol DU Dept Comp Engn Pune 411025 Maharashtra India Wayne State Univ Dept Elect & Comp Engn Detroit MI 48202 USA

The real-time nondestructive testing (NDT) for crack detection and impact source identification (CDISI) has attracted the researchers fromdiverse areas. This is apparent fromthe current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposedmethod can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB's fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL). The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA) implementation is done using Xilinx's Spartan 3 FPGA. SynaptiCAD's Verilog Simulators-VeriLogger PRO andModelSim-are used as the software simulation and debug environment.

关键词： Hardware description language Soft computing Nondestructive testing Crack field-programmable gate array Fuzzy logic

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Studies of Forward Projection Algorithms and Implementation on PC and FPGA

Studies of Forward Projection Algorithms and Implementation ...

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作者： Cho, Minsung University of Nevada Las Vegas

学位级别：M.S.E., Master of Science in Engineering/Education

This thesis first aims to understand how a part of the computed tomography (CT) algorithm called “forward projector” (FP) works and how it can be accelerated at a hardware level. Two methods of FP are defined and studied: pixel-driven and ray-driven. Both methods fundamentally use the property of line integral and Bresenham’s algorithm. As the result of the study of the two FP methods, the ray-driven algorithm implemented in C++ performed 35% faster than the pixe-driven algorithm implemented in Python. This thesis implements the ray-driven forward projector algorithm using field-programmable gate array (FPGA), making use of hardware-acceleration techniques. The result shows that the FPGA implementation had a comparable speed advantage compared to the implementation on the personal computer (PC). Even though the FPGA used was outdated and budget-oriented, the chip was able to perform 58% of the performance of a more expensive, modern, and performance-oriented PC. Also, the FPGA implementation performed better in power consumption compared to the PC. Methodologies included the state machine, random access memory (RAM), and universal asynchronous receiver-transmitter (UART). By using the results in this thesis, a CT scanner can be designed to be less expensive, more efficient, faster, and use less power.

关键词： Forward projector Computed tomography field-programmable gate array Personal computer

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Human Activity Recognition Based on Point Clouds from Millimeter-Wave Radar

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APPLIED SCIENCES-BASEL 2024年第22期14卷 10764页

作者： Lim, Seungchan Park, Chaewoon Lee, Seongjoo Jung, Yunho Korea Aerosp Univ Sch Elect & Informat Engn Goyang 10540 South Korea Sejong Univ Dept Elect Engn Seoul 05006 South Korea Sejong Univ Dept Convergence Engn Intelligent Drone Seoul 05006 South Korea Korea Aerosp Univ Dept Smart Air Mobil Goyang 10540 South Korea

Human activity recognition (HAR) technology is related to human safety and convenience, making it crucial for it to infer human activity accurately. Furthermore, it must consume low power at all times when detecting human activity and be inexpensive to operate. For this purpose, a low-power and lightweight design of the HAR system is essential. In this paper, we propose a low-power and lightweight HAR system using point-cloud data collected by radar. The proposed HAR system uses a pillar feature encoder that converts 3D point-cloud data into a 2D image and a classification network based on depth-wise separable convolution for lightweighting. The proposed classification network achieved an accuracy of 95.54%, with 25.77 M multiply-accumulate operations and 22.28 K network parameters implemented in a 32 bit floating-point format. This network achieved 94.79% accuracy with 4 bit quantization, which reduced memory usage to 12.5% compared to existing 32 bit format networks. In addition, we implemented a lightweight HAR system optimized for low-power design on a heterogeneous computing platform, a Zynq UltraScale+ ZCU104 device, through hardware-software implementation. It took 2.43 ms of execution time to perform one frame of HAR on the device and the system consumed 3.479 W of power when running.

关键词： millimeter-wave radar 3D point cloud human activity recognition field-programmable gate array

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FPGA Implementation for 24.576-Gbit/s Optical PAM4 Signal Transmission with MLP-Based Digital Pre-Distortion

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SENSORS 2024年第23期24卷 7872页

作者： Hu, Sheng Zheng, Tianqi Bian, Chengzhen Yang, Xiongwei Sun, Xinda Zhu, Zonghui Gou, Yumeng Meng, Yuanxiao Zhang, Jie Ge, Jingtao Li, Yichen Wang, Kaihui Fudan Univ State Key Lab Integrated Chips & Syst Shanghai 200433 Peoples R China

In this work, we implemented a short-reach real-time optical communication system using MLP for pre-distortion. Lookup table (LUT) algorithms are commonly employed for pre-distortion in intensity modulation and direct detection (IM/DD) systems. However, storage limitations typically restrict the LUT pattern length to 9, limiting its effectiveness in compensating for nonlinear effects. A multilayer perceptron (MLP) can overcome this limitation by predicting errors and generating pre-distorted signals, thus replacing the extensive storage requirements of LUTs with minimal computational resources. The MLP-based digital pre-distortion (MLP-DPD) technique enables the creation of long-pattern LUTs for improved nonlinear compensation. In this work, an MLP-DPD scheme was implemented on a field-programmable gate array (FPGA). The FPGA was used to generate a 14.7456 GBaud pre-distorted pulse amplitude modulation 4-level (PAM4) signal. This signal was then transmitted over 20 km of standard single-mode fiber (SSMF). At the receiver, the parallel constant modulus algorithm (PCMA) was applied for signal processing. The bit error rate (BER) achieved met the 2.4 x 10-2 threshold for soft-decision forward error correction (SD-FEC), enabling a net transmission bit rate of 24.576 Gbit/s. This approach demonstrates the feasibility of using MLP-DPD for effective nonlinear compensation in high-speed optical communication systems with limited resources.

关键词： digital pre-distortion real-time communication field-programmable gate array pulse amplitude modulation 4-level intensity modulation direct detection

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