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Event management for large scale event-driven digital hardware spiking neural networks

NEURAL NETWORKS 2013年 45卷 83-93页

作者： Caron, Louis-Charles D'Haene, Michiel Mailhot, Frederic Schrauwen, Benjamin Rouat, Jean Univ Sherbrooke NECOTIS Sherbrooke PQ J1K 2R1 Canada Univ Ghent Reservoir Lab B-9000 Ghent Belgium

The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65 536 neurons and 513 184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406 x 158 pixel image is segmented in 200 ms. (C) 2013 Elsevier Ltd. All rights reserved.

关键词： Neuromorphic engineering field-programmable gate array Pipelined heap queue Event-driven simulation Spiking neural network

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Frequency domain near-infrared multiwavelength imager design using high-speed, direct analog-to-digital conversion

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JOURNAL OF BIOMEDICAL OPTICS 2016年第1期21卷 1-8页

作者： Zimmermann, Bernhard B. Fang, Qianqian Boas, David A. Carp, Stefan A. Harvard Med Sch Massachusetts Gen Hosp Athinoula A Martinos Ctr Biomed Imaging Bldg 14913th St Charlestown MA 02129 USA MIT Dept Elect Engn & Comp Sci 77 Massachusetts Ave Cambridge MA 02139 USA Northeastern Univ Dept Bioengn 360 Huntington Ave Boston MA 02115 USA

Frequency domain near-infrared spectroscopy (FD-NIRS) has proven to be a reliable method for quantification of tissue absolute optical properties. We present a full-sampling direct analog-to-digital conversion FD-NIR imager. While we developed this instrument with a focus on high-speed optical breast tomographic imaging, the proposed design is suitable for a wide-range of biophotonic applications where fast, accurate quantification of absolute optical properties is needed. Simultaneous dual wavelength operation at 685 and 830 nm is achieved by concurrent 67.5 and 75 MHz frequency modulation of each laser source, respectively, followed by digitization using a high-speed (180 MS/s) 16-bit A/D converter and hybrid FPGA-assisted demodulation. The instrument supports 25 source locations and features 20 concurrently operating detectors. The noise floor of the instrument was measured at <1.4 pW/root Hz, and a dynamic range of 115+ dB, corresponding to nearly six orders of magnitude, has been demonstrated. Titration experiments consisting of 200 different absorption and scattering values were conducted to demonstrate accurate optical property quantification over the entire range of physiologically expected values. (C) 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： radio frequency diffuse near-infrared light full sampling field-programmable gate array absolute optical property breast cancer

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Performance evaluation of FPGA-based predictive current controller for FL-DSTATCOM in electric distribution system

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IET GENERATION TRANSMISSION & DISTRIBUTION 2019年第19期13卷 4400-4409页

作者： Dheepanchakkravarthy, Azhagesan Jawahar, Marappan Rakkiannan Venkatraman, Kandadai Selvan, Manickavasagam Parvathy Moorthi, Sridharan Bannari Amman Inst Technol Dept Elect & Elect Engn Sathyamangalam India Natl Inst Technol Dept Elect & Elect Engn Hybrid Elect Syst Lab Tiruchirappalli 620015 Tamil Nadu India Vardhaman Coll Engn Dept Elect & Elect Engn Hyderabad India

A four-leg distribution static compensator (FL-DSTATCOM) has been employed for improving the quality of power in electric distribution system using field-programmable gate array (FPGA). A predictive current control technique without any modulation scheme is utilised to generate switching pulses for FL-DSTATCOM using a cost function defining the preferred system behaviour. This technique makes the supply current as balanced and sinusoidal by exactly tracking the reference current, compensating the reactive power, maintaining near unity power factor and nullifies the current flow in neutral conductor during steady and dynamic state conditions. Synchronous reference frame theory is effectively implemented for extracting the reactive and harmonic part of load current which are the primary components in the evaluation of reference currents. The predictive current control scheme implemented in FPGA has been deployed to evaluate the behaviour of the FL-DSTATCOM under multifarious loading conditions.

关键词： field programmable gate arrays predictive control power factor electric current control static VAr compensators power distribution control digital control power supply quality reactive power FL-DSTATCOM electric distribution system four-leg distribution static compensator field-programmable gate array supply current unity power factor current flow load current performance evaluation FPGA-based predictive current controller system behaviour reactive power compensation power quality switching pulse generation cost function reference current tracking neutral conductor dynamic state conditions steady state conditions synchronous reference frame theory reference current evaluation multifarious loading conditions near unity power factor

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A resource saving FPGA implementation approach to fractional Kalman filter

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IET CONTROL THEORY AND APPLICATIONS 2022年第13期16卷 1352-1363页

作者： Xu, Bo Bai, Libing Chen, Kai Tian, Lulu Univ Elect Sci & Technol China Sch Automat Engn Chengdu 611731 Peoples R China

The efficiency of the hardware implementations of fractional Kalman filter (FKF) heavily relies on the efficiency of realising the fractional-order derivative operator. In this paper, a generic software and hardware implementation of the FKF based on the Grunwald-Letnikov approximation is proposed and verified on a field-programmable gate array. The main advantage of this particular realisation is its resource saving capability on both software and hardware components (e.g. digital signal processing chips), and this enables fast and efficient real-time computation of the FKF. Furthermore, the performance of the FKF is evaluated via studying the mean square boundedness of the filtering error. At last, a mass-spring-damper example is implemented via Matlab simulations to verify the applicability of the proposed approach and moreover, a hardware experiment is also conducted to demonstrate the advantage of resource saving.

关键词： digital signal processing chips software components hardware experiment filtering error Grunwald-Letnikov approximation field-programmable gate array FKF generic software hardware implementation fractional-order derivative operator field programmable gate arrays fractional Kalman filter approximation theory particular realisation hardware-software codesign FPGA implementation approach mean square boundedness hardware components hardware implementations mass-spring-damper Matlab simulations Kalman filters

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PROSPECTS FOR RECONFIGURABLE SYSTEMS

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IEEE MICRO 2014年第1期34卷 72-78页

作者： Tredennick, Nick Shimamoto, Brion Univ Texas Austin Austin TX 78712 USA Univ Calif Los Angeles Los Angeles CA USA

IN 2003, THE AUTHORS PREDICTED THAT RECONFIGURABLE SYSTEMS WOULD EMERGE WITHIN 10 YEARS. THEY EXPECTED THE ARRIVAL OF A "HOLY GRAIL" MEMORY COMPONENT AND CHIP AND WAFER STACKING. THESE ADVANCES DID NOT OCCUR. RECONFIGURABLE SYSTEMS SHOULD APPEAR IN MARKETS WHERE EQUIPMENT HAS ACCESS TO CONTINUOUS POWER, BUT FINANCIAL INCENTIVES AND THE LACK OF A VERSATILE MEMORY COMPONENT INHIBIT THEIR EMERGENCE IN MOBILE SYSTEMS.

关键词： field programmable gate arrays field-programmable gate array FPGA Mobile handsets Random access memory Reconfigurable architectures reconfigurable computing reconfigurable systems Signal processing algorithms Transistors value PC value transistor

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Implementation of modulation classifier over software defined radio

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IET COMMUNICATIONS 2020年第9期14卷 1467-1475页

作者： Jajoo, Gaurav Kumar, Yogesh Kumar, Ashok Yadav, Sandeep Kumar Dept Elect Engn NH 65 Jodhpur Rajasthan India DRDO Sci Anal Grp Sag Delhi India

Blind signal modulation recognition is an essential block for designing a cognitive radio. Different algorithms are developed in the literature, but few are given with detailed implementation. This study proposes a software-defined radio based implementation of blind signal modulation recogniser (BSMR) on field-programmable gate array (FPGA), which works without any prior knowledge of the received signal. The algorithm estimates carrier frequency offset, symbol rate, symbol timing offset, and corrects the signal for these offsets to extract constellation points. It uses clustering structure formed by constellation signature in I/Q plane to detect the modulation for different orders of ASK, PSK, and QAM. The proposed algorithm is deployed on FPGA, using LabVIEW, for a reliable and reconfigurable platform. The algorithm is optimised to use minimum hardware resources and facilitate future up-gradation. The system developed by implementing the algorithm on NI-FlexRIO-7975 FPGA module with NI-5791 adapter detects modulation type in real time without any training. Signals for testing are generated using NI-PXIe-5673 (RF transmitter), and BSMR identifies the modulation type in 81.451ms under additive white Gaussian noise channel.

关键词： virtual instrumentation phase shift keying cognitive radio field programmable gate arrays quadrature amplitude modulation AWGN channels software radio amplitude shift keying pattern classification pattern clustering BSMR modulation classifier blind signal modulation recognition cognitive radio software-defined radio blind signal modulation recogniser field-programmable gate array received signal carrier frequency offset symbol rate symbol timing offset constellation points constellation signature NI-FlexRIO-7975 FPGA module NI-5791 adapter clustering structure ASK PSK QAM LabVIEW reconfigurable platform RF transmitter additive white Gaussian noise channel

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Ion current-based homogeneous charge compression ignition combustion control using direct water injection

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INTERNATIONAL JOURNAL OF ENGINE RESEARCH 2021年第6期22卷 1825-1837页

作者： Zhu, Denghao Deng, Jun Dewor, Raphael Wick, Maximilian Andert, Jakob Li, Liguang Tongji Univ Shanghai 201804 Peoples R China Rhein Westfal TH Aachen Inst Tech Thermodynam Aachen Germany FEV Europe GmbH Aachen Germany Rhein Westfal TH Aachen Mechatron Syst Combust Engines Aachen Germany

Homogeneous charge compression ignition has proven to be both highly efficient and to operate with ultra-low NOx raw emissions. However, homogeneous charge compression ignition combustion is a dynamic process due to strong cycle-to-cycle coupling effects caused mainly by the residual gas. Compared to conventional spark-ignited and diesel engines, the lack of direct mixture composition and ignition control increases the challenge of combustion instabilities, especially at boundary conditions. To stabilize the combustion process, real-time in-cylinder combustion diagnostics and control are often used. In this study, for the first time, ion current detection technology and direct water injection are combined for homogeneous charge compression ignition combustion control. By analyzing the return map of the crank angle at 50% cumulative heat release under unstable conditions, it was identified that a misfire or incomplete combustion is usually followed by knocking-like early combustion with high cylinder pressure gradients. Through the correlation analysis between ion current and combustion, a cycle-to-cycle closed-loop control strategy was developed and implemented on a rapid control prototyping engine control unit. Real-time calculated ion current parameters were used to predict the 50% cumulative heat release position of the next cycle and prevent early combustion by direct water injection. The calculation results and controller performance were validated on a single-cylinder research engine. With the controller activated, the standard deviation of 50% cumulative heat release and dynamic programming to the max could be reduced by 19% and 11%, respectively. The coefficient of variation of indicated mean effective pressure was reduced by 12%. A slight increase in indicated mean effective pressure after activating the controller also shows the potential for efficiency improvement. Moreover, not only early combustion is controlled, but also late combustion is significantl

关键词： Ion current homogeneous charge compression ignition gasoline controlled autoignition field-programmable gate array combustion control water injection

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A compact hardware architecture for digital image stabilization using integral projections

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MICROPROCESSORS AND MICROSYSTEMS 2015年第8期39卷 987-997页

作者： Araneda, Luis Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Ctr Opt & Photon CEFOP Concepcion Chile

We present a hardware architecture for real-time digital video stabilization for high-performance embedded systems. The stabilization algorithm analyzes the current and past video frames and obtains a motion estimation vector, which is then filtered to isolate unwanted camera movements from intentional panning. The vector is then used to correct the output video frame. The paper describes our hardware architecture for motion estimation, filtering and correction and its implementation on a Xilinx Spartan-6 LX45 FPGA. We evaluate our results on several benchmark video sequences, both visually and using the Inter-frame Transformation Fidelity index (ITF). Running on the 640 x 480-pixel video output of an infrared camera, our FPGA implementation successfully compensates involuntary camera motion at a maximum throughput of 104.15 frames per second with a 100 MHz clock. The power consumption added to the FPGA by the image stabilization core is only 24.16 mW. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Embedded video processing field-programmable gate array Digital image stabilization Integral projections

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Dual-model predictive control of two independent induction motors driven by a SiC nine-switch inverter

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INTERNATIONAL JOURNAL OF ELECTRONICS 2023年第1期110卷 124-142页

作者： Gokdag, Mustafa Gulbudak, Ozan Karabuk Univ Dept Elect Elect Engn Karabuk Turkey

This paper presents a finite control set model predictive control (FCS-MPC) approach for two induction machines driven by a nine-switch inverter (NSI). In the traditional approach, two separate voltage source inverters are necessary to drive the independent induction motors. In the proposed method, the nine-switch inverter is used to control the separate motors with a reduced number of switching devices compared to traditional method. A robust control strategy that eliminates the interactions between separate mechanical loads is required to achieve a proper independent speed and torque control for two induction machines through the NSI. To ensure the reliability of the machine operation, the indirect-field oriented control-based model predictive control strategy is proposed. The proposed control strategy is experimentally validated across the 3.2 kW SiC-based NSI prototype. The control algorithm is performed on an Altera Cyclone IV field-programmable gate array. The experimental results demonstrate that the proposed dual-model predictive control method provides a good and robust motor control operation under different loading conditions. Two induction motors are successfully controlled, and the independent speed and torque control are achieved.

关键词： Nine-switch inverter multi-drive systems multi-machines model predictive control indirect field-oriented control field-programmable gate array

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Resource-constrained FPGA/DNN co-design

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NEURAL COMPUTING & APPLICATIONS 2021年第21期33卷 14741-14751页

作者： Zhang, Zhichao Kouzani, Abbas Z. Deakin Univ Sch Engn Geelong Vic 3216 Australia

Deep neural networks (DNNs) have demonstrated super performance in most learning tasks. However, a DNN typically contains a large number of parameters and operations, requiring a high-end processing platform for high-speed execution. To address this challenge, hardware-and-software co-design strategies, which involve joint DNN optimization and hardware implementation, can be applied. These strategies reduce the parameters and operations of the DNN, and fit it into a low-resource processing platform. In this paper, a DNN model is used for the analysis of the data captured using an electrochemical method to determine the concentration of a neurotransmitter and the recoding electrode. Next, a DNN miniaturization algorithm is introduced, involving combined pruning and compression, to reduce the DNN resource utilization. Here, the DNN is transformed to have sparse parameters by pruning a percentage of its weights. The Lempel-Ziv-Welch algorithm is then applied to compress the sparse DNN. Next, a DNN overlay is developed, combining the decompression of the DNN parameters and DNN inference, to allow the execution of the DNN on a FPGA on the PYNQ-Z2 board. This approach helps avoid the need for inclusion of a complex quantization algorithm. It compresses the DNN by a factor of 6.18, leading to about 50% reduction in the resource utilization on the FPGA.

关键词： Lempel-Ziv-Welch compression Deep neural network Hardware-and-software co-design Electrochemical sensing field-programmable gate array

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