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65th IEEE Autotestcon Conference (IEEE AUTOTESTCON)

作者： Don, Michael Schomer, Nathan Grabner, Mitchell Miller, Cory Hallameyer, Jonathan DEVCOM Army Res Lab Weap & Mat Res Directorate Aberdeen Proving Ground MD 21005 USA SURVICE Engn Co 4695 Millennium Dr Belcamp MD USA

ISBN: (纸本)9781728154008

The DEVCOM Army Research Laboratory has redesigned its Multi-functional Instrumentation and Data Acquisition System (MIDAS) to support an embedded Linux-based flight controller for its smart munitions research. This includes field-programmable gate array development of a serial peripheral interface between the sensor board and flight controller, integration of three new digital sensors using a soft-core processor, and the design of a custom Linux software stack. This new version of MIDAS has been successfully used in several flight experiments, and will continue to support future smart munitions research and development.

关键词： instrumentation data acquisition embedded software field-programmable gate array flight control

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Power Electronics Control with System-on-a-Chip-Based Platforms 20

Power Electronics Control with System-on-a-Chip-Based Platfo...

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IEEE 20th International Power Electronics and Motion Control Conference (PEMC)

作者： Guerreiro, Marco Kharade, Shrikant dos Santos, Pedro Liu, Steven Tech Univ Kaiserslautern Chair Control Syst Kaiserslautern Germany

ISBN: (数字)9781665496810

ISBN: (纸本)9781665496810

An emerging trend in power electronics control is the use of controllers based on a system-on-a-chip (SoC). SoCs provide a high-performance computing platform by embedding one or multiple processors and a field-programmable gate array (FPGA) on the same chip. This paper reviews SoCs for power electronics control applications, discussing aspects such as task allocations and available hardware and software tools. A design and experimental results of an SoC-based controller are discussed, and some of the SoC-based platforms built by researchers in power electronics control are reviewed.

关键词： power electronics embedded control system-on-a-chip field-programmable gate array

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FPGA implementation of LSD-OMP for real-time ECG signal reconstruction

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2021年第4期29卷 1887-1907页

作者： Polat, Onder Kayhan, Sema Koc Gaziantep Univ Elect & Elect Engn Dept Fac Engn Gaziantep Turkey

Compressed sensing is widely used to compress electrocardiogram (ECG) signals, but the major challenges of the compressed sensing algorithms are their highly complex signal reconstruction processes. In this paper, a re-configurable high-speed and low-power field-programmable gate array (FPGA) implementation of the least support denoising-orthogonal matching pursuit (LSD-OMP) algorithm for the real-time reconstruction of the ECG signals is pre-sented. The contribution of this study is two-fold: Firstly, LSD-OMP can pick more than one element at each iteration and reconstruct the sparse signal using less number of iterations as compared to the standard OMP algorithms. Latency of the proposed design is therefore reduced by exploiting the multiple index selection feature of LSD-OMP. Secondly, the proposed architecture is the first reconfigurable LSD-OMP reconstruction architecture which can take different signal sizes and different sparsity levels. The proposed design also includes an efficient inverse wavelet transform (IWT) module to convert the reconstructed signal back into the time-domain. Together with the overhead of the IWT module, the proposed design demonstrates faster execution times while consuming lower power than the existing FPGA implemen-tations;therefore, it can be utilized in wireless body area networks as a back-end unit to reconstruct the compressed ECG signals.

关键词： field-programmable gate array electrocardiogram real-time compressed sensing

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Systolic Architectures for Efficient Deep Neural Network Implementations with Assured Performance

Systolic Architectures for Efficient Deep Neural Network Imp...

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作者： Zhang, Sai Qian Harvard University

学位级别：Ph.D.

Deep neural networks (DNNs) have gained major interests in a variety of application domains including computer vision, natural language processing, autonomous driving, etc. While DNNs deliver state-of-the-art accuracies on many AI tasks, they comes at the cost of high computational complexity. Accordingly, designing efficient hardware architectures for DNNs is an important step towards enabling the wide deployment of DNNs in the modern AI system. Although DNNs have been developed to solve a variety of problems, the major arithmetic operations involved in these DNNs are almost identical: a series of matrix multiplications between the inputs and the DNN weights. Therefore, an efficient hardware architecture for supporting matrix operations plays a key role in DNN implementations. Systolic arrays are widely known to be appealing for matrix multiplication operation due to their regular layout of processing elements, efficient interprocessor communication, and reduced memory access. This has led to numerous commercial DNN accelerators using systolic arrays for matrix multiplication (e.g., Google Tensor Processing Unit). In this thesis, we explore innovative systolic architectures that support DNN executions at low cost. We leverage the recent advances in DNN pruning (removing superfluous parameters from DNNs) and DNN quantization (converting the high-precision DNN parameters into low-precision parameters), and describe (1) techniques to overcome the limitation of systolic arrays in addressing sparse matrices of irregular sparsity structures and in addressing load balancing over systolic cells, and (2) new uses of systolic arrays in DNNs. By evaluating the novel systolic architectures with both Application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA), we demonstrate the superior performance of our systolic designs in terms of both processing latency and energy efficiency across multiple DNN models and datasets. In addition to the evaluation

关键词： Deep neural networks Application-specific integrated circuit field-programmable gate array

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Low-Resource Time-to-Digital Converters for field programmable gate arrays: A Review

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SENSORS 2024年第17期24卷 5512页

作者： Real, Diego Calvo, David Univ Valencia IFIC Inst Fis Corpuscular CSIC C Catedrat Jose Beltran 2 Paterna 46980 Spain

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within field-programmable gate arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process-Voltage-Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field.

关键词： time-to-digital converter field-programmable gate array low-resource time-to-digital converters

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Ergodic sequential logic spiking neural network: reproductions of biologically plausible spatio-temporal phenomena and low-power implementation towards neural prosthesis

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IEICE ELECTRONICS EXPRESS 2024年第8期21卷 20240095-20240095页

作者： Shiomi, Yuta Torikai, Hiroyuki Hosei Univ Grad Sch Sci & Engn Koganei Tokyo 1848485 Japan

A spiking neural network of ergodic sequential logic neuron models is presented. It is shown that the presented network is capable of reproducing various biologically plausible spatio-temporal phenomena (e.g., basic synchronization and complicated chimera phenomenon) observed in the brain. Moreover, it is revealed that the presented network is able to operate with lower power compared to a standard digital -processor -based spiking neural network. It is then discussed that the presented network will be a useful building block in a brain prosthetic device.

关键词： neural prosthesis ergodic sequential logic cellular automaton field-programmable gate array

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FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年

作者： Li, Tenglong Li, Jindong Shen, Guobin Zhao, Dongcheng Zhang, Qian Zeng, Yi Univ Chinese Acad Sci Sch Artificial Intelligence Beijing 100049 Peoples R China Chinese Acad Sci Inst Automat Brain Inspired Cognit Intelligence Lab Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Future Technol Beijing 100049 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Chinese Acad Sci Key Lab Brain Cognit & Brain Inspired Intelligence Shanghai 200031 Peoples R China

Spiking Neural Networks (SNNs), with their brain-inspired structure using discrete spikes instead of continuous activations, are gaining attention for their potential of efficient processing on neuromorphic chips. While current SNN hardware accelerators often prioritize temporal spike sparsity, exploiting sparse synaptic weights offers significant untapped potential for even greater efficiency. To address this, we propose FireFly-S, a Sparse extension of the FireFly series. This co-optimized software-hardware design focusing on leveraging dual-side sparsity for acceleration. On the software side, we propose a novel algorithmic optimization framework that combines gradient rewiring for pruning and modified Learned Step Size Quantization (LSQ) tailored for SNNs, which achieves remarkable weight sparsity exceeding 85% and enables efficient 4-bit quantization with negligible accuracy loss. On the hardware side, we present an efficient dual-side sparsity detector employing a Bitmap-based sparse decoding logic to pinpoint the positions of non-zero weights and input spikes. The logic allows for the direct bypassing of redundant computations, thereby enhancing computational efficiency. Different from the overlay architecture adopted by previous FireFly series, we adopt a parametric spatial architecture with inter-layer pipelining that can fully exploit the fine-grained programmability and reconfigurability of field-programmable gate arrays (FPGAs), enabling fast deployment for various models. A spatial-temporal dataflow is also proposed to support such inter-layer pipelining and avoid long-term temporal dependencies. In experiments conducted on the MNIST, DVS-Gesture and CIFAR-10 datasets, the FireFly-S model achieves 85-95% sparsity with 4-bit quantization and the hardware accelerator effectively leverages the dual-side sparsity, delivering outstanding performance metrics of 10,047 FPS/W on MNIST, 3,683 FPS/W on DVS-Gesture, and 2,327 FPS/W on CIFAR-10.

关键词： Spiking neural networks field-programmable gate array hardware accelerator dual-side sparsity software-hardware co-design inter-layer pipelining

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Optimal Selection of Switch Model Parameters for ADC-Based Power Converters

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ENERGIES 2024年第1期17卷 56页

作者： Alsarayreh, Saif Suto, Zoltan Budapest Univ Technol & Econ Dept Automat & Appl Informat Muegyet Rkp 3 H-1111 Budapest Hungary

Real-time hardware-in-the-loop-(HIL) simulation integration is now a fundamental component of the power electronics control design cycle. This integration is required to test the efficacy of controller implementations. Even though hardware-in-the-loop-(HIL) tools use FPGA devices with computing power that is rapidly evolving, developers constantly need to balance the ease of deploying models with acceptable accuracy. This study introduces a methodology for implementing a full-bridge inverter and buck converter utilising the associate-discrete-circuit-(ADC) model, which is optimised for real-time simulator applications. Additionally, this work introduces a new approach for choosing ADC parameter values by using the artificial-bee-colony-(ABC) algorithm, the firefly algorithm (FFA), and the genetic algorithm (GA). The implementation of the ADC-based model enables the development of a consistent architecture in simulation, regardless of the states of the switches. The simulation results demonstrate the efficacy of the proposed methodology in selecting optimal parameters for an ADC-switch-based full-bridge inverter and buck converter. These results indicate a reduction in overshoot and settling time observed in both the output voltage and current of the chosen topologies.

关键词： associate discrete circuit real-time simulation field-programmable gate array optimisation algorithm power converters

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Real-time FPGA Integration for ECG Monitoring: Bidirectional Recurrent Chimp Search Model

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IETE JOURNAL OF RESEARCH 2024年第8期70卷 6848-6863页

作者： Shanthi, K. G. Kinol, A. Mary Joy Santhi, S. Kannan, K. RMK Coll Engn & Technol Dept Elect & Commun Engn Chennai Tamil Nadu India Saveetha Univ Saveetha Inst Med & Tech Sci Saveetha Sch Engn Dept Elect & Commun Engn Chennai Tamil Nadu India KIT Kalaignarkarunanidhi Inst Technol Dept Comp Sci & Engn Coimbatore Tamil Nadu India

The primary diagnostic tool for monitoring problems with the heart or related diseases is the electrocardiogram (ECG). The rising mortality rate caused by cardiac abnormalities leads to the development of more advanced techniques to detect heart anomalies are is of paramount importance. An electrocardiogram (ECG) is used for multiple diagnostic purposes since it produces continuous tracings of the electrophysiological activity generated from the heart. This paper developed a Bidirectional recurrent chimp search (Bi-RCS) method for diagnosing abnormalities by collecting ECG signals via various phases such as the data acquisition phase, signal processing phase, feature extraction phase, abnormality detection phase, real-time FPGA integration phase, monitoring and reporting phase as well as feedback phase. Signal pre-processing removes contaminants like noise using the Adaptive filtering methodology which severely limits the utility of the recorded ECG for better clinical evaluation. Bi-RNN is utilized for extracting related features and detecting abnormalities and the Chimp search optimization is employed to tune the parameters of Bi-RNN. After detecting the abnormalities, the reports of patients are monitored and recorded to provide an alert signal to healthcare providers. Finally, the potency of the methodology is analyzed with the ECG signal dataset and metrics like precision, F1-score accuracy, sensitivity, and specificity values. The obtained outputs equalized with the existing methods like KNN, EBT, and SVM. The analysis showed convincing performance with an accuracy of 99% and less error rate of 0.05.

关键词： Adaptive filtering Bidirectional Recurrent Neural Network Chimps optimization Electrocardiogram field-programmable gate array

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Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices 1

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18th International Symposium on Applied Reconfigurable Computing

作者： Rognlien, Markus Que, Zhiqiang Coutinho, Jose G. F. Luk, Wayne Imperial Coll London Dept Comp 180 Queens Gate London England

ISBN: (数字)9783031199837

ISBN: (纸本)9783031199820;9783031199837

AI solutions, such as Deep Learning (DL), are becoming increasingly prevalent in edge devices. Many of these applications require low latency processing of large amounts of data within a tight power budget. In this context, reconfigurable embedded devices make a compelling option. Deploying DL models to reconfigurable devices does, however, present considerable challenges. One key issue is reconciling the often large compute requirements of DL models with the limited available resources on edge devices. In this paper, we present a hardware-aware optimization strategy for deploying DL neural networks to FPGAs, which automatically identifies hardware configurations that maximize resource utilization for a given level of computation throughput. We demonstrate our optimization approach on a sample neural network containing a combination of convolutional and fully connected layers, running on a sample FPGA target device, achieving a factor of 3.5 reduction in DSP block usage without affecting throughput when using performance mode. When using the compact mode, a factor of 7.4 reduction in DSP block usage is achieved, at the cost of 1.8 times decrease in throughput. Our approach works completely automatically without the need for human intervention or domain knowledge.

关键词： field-programmable gate array High-level synthesis Meta-programming Particle physics

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