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Si APD-Based High Speed Infrared Radiation Thermometry for Analysing the Temperature Instability of a Combustion Chamber

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SENSORS 2024年第23期24卷 7780页

作者： Karapateas, Louis Lai, Yufeng Meng, Xiangfei Zhang, Yang Willmott, Jon R. Hobbs, Matthew J. Univ Sheffield Portobello Ctr Sch Elect & Elect Engn Sensor Syst Grp Pitt St Sheffield S14 ET England Univ Sheffield Sch Mech Aerosp & Civil Engn Sir Frederick Mappin BldgMappin St Sheffield S1 3JD England

This study introduces a novel approach to analysing the combustion process using a high-speed, non-contact, optical fibre-coupled Si avalanche photodiode (APD)-based infrared radiation thermometer (IRT). The Si APD-IRT, combined with an optimised field-programmable gate array (FPGA)-based digital design, achieves a response time of 1 mu s, faster than commercially available instruments. Our instrument captures the entire ignition and reignition cycle of a Jet A kerosene droplet with high temporal precision within a combustion chamber, a feat impossible with traditional thermocouples. The FPGA module was validated with a 1 mu s data acquisition time, using a 40 MHz onboard clock, achieving throughput of 0.64 Gbps with efficiencies of 0.062 Mbps/slice in lookup tables (LUTs), confirming a low-area design compared to conventional FPGAs. The IRT achieves a root mean square (RMS) noise specification of 0.5 degrees C at a 1 mu s acquisition time and a target temperature of approximately 1000 degrees C. A measurement uncertainty of within +/- 0.25% degrees C + 2 degrees C confirms that it lies within the bounds of commercial instrumentations. Our instrument was demonstrated to capture transient temperature fluctuations during combustion and characterises Jet A kerosene fuel droplets, laying the foundation for understanding sustainable aviation fuels (SAFs) and their role in transitioning from aviation fossil fuels, enabling effective research and development.

关键词： avalanche photodiode droplet combustion ignition infrared radiation thermometry field-programmable gate array

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FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

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ENERGIES 2024年第8期17卷 1870页

作者： Wu, Caiyun Zhang, Kai Zhang, Xin Shenyang Ligong Univ Sch Equipment Engn Shenyang 110159 Peoples R China Shenyang Ligong Univ Sch Automot & Transportat Shenyang 110159 Peoples R China

To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional-integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed.

关键词： PMSM control system beetle antennae search field-programmable gate array intelligent optimization algorithm

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Miniaturization Design of High-Integration Unmanned Aerial Vehicle-Borne Video Synthetic Aperture Radar Real-Time Imaging Processing Component

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REMOTE SENSING 2024年第7期16卷 1273页

作者： Yang, Tao Wang, Tong Zheng, Nannan Zhang, Shuangxi Meng, Fanteng Zhang, Xinyu Wu, Qirui Xidian Univ Sch Aerosp Sci & Technol Xian 710126 Peoples R China Northwestern Polytech Univ Sch Elect & Informat Xian 710129 Peoples R China

The unmanned aerial vehicle (UAV)-borne video synthetic aperture radar (SAR) possesses the characteristic of having high-continuous-frame-rate imaging, which is conducive to the real-time monitoring of ground-moving targets. The real-time imaging-processing system for UAV-borne video SAR (ViSAR) requires miniaturization, low power consumption, high frame rate, and high-resolution imaging. In order to achieve high-frame-rate real-time imaging on limited payload-carrying platforms, this study proposes a miniaturization design of a high-integration UAV-borne ViSAR real-time imaging-processing component (MRIPC). The proposed design integrates functions such as broadband signal generation, high-speed real-time sampling, and real-time SAR imaging processing on a single-chip FPGA. The parallel access mechanism using multiple sets of high-speed data buffers increases the data access throughput and solves the problem of data access bandwidth. The range-Doppler (RD) algorithm and map-drift (MD) algorithm are optimized using parallel multiplexing, achieving a balance between computing speed and hardware resources. The test results have verified that our proposed component is effective for the real-time processing of 2048 x 2048 single-precision floating-point data points to realize a 5 Hz imaging frame rate and 0.15 m imaging resolution, satisfying the requirements of real-time ViSAR-imaging processing.

关键词： video synthetic aperture radar real-time imaging field-programmable gate array range-Doppler algorithm map-drift algorithm

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FPGA-based Reservoir Computing with Optimized Reservoir Node Architecture 23

FPGA-based Reservoir Computing with Optimized Reservoir Node...

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23rd International Symposium on Quality Electronic Design (ISQED)

作者： Lin, Chunxiao Liang, Yibin Yi, Yang Virginia Tech Bradley Dept Elect & Comp Engn Blacksburg VA USA

ISBN: (纸本)9781665494663

Updating the state of reservoir nodes is one of the essential operations of reservoir computing (RC), which highly affects the system's performance. In an echo state network (ESN), one of the primary types of RC, the process of state renewal can be divided into two stages: multiplication of the weight matrix with the input-state vector and applying a nonlinear activation function on the sum of products. The weight matrix is typically large and sparse, providing opportunities for optimizing the matrix multiplication;the choices of activation functions may also affect hardware resource utilization. This paper introduces an optimized reservoir node architecture for FPGA-based RC systems. Specifically, we adopt the bit-serial matrix multiplier and direct spatial implementation of the weight matrix to fully exploit the sparseness property. The canonical signed digit representation is also employed to further optimize the multiplier logic. Furthermore, a hyperbolic tangent activation function is designed and optimized to maintain the nonlinearity of the neural network without affecting its accuracy. Compared with existing hardware ESN designs, our reservoir node architecture significantly reduces resource utilization while maintaining comparable performance.

关键词： Reservoir computing field-programmable gate array echo state network architecture

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An FPGA Hardware-in-the-Loop Approach for Comprehensive Analysis and Development of Grid-Connected VSI System

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ENERGIES 2023年第2期16卷 759页

作者： Singh, Vijay Kumar Tripathi, Ravi Nath Rajiv Gandhi Inst Petr Technol Dept Elect Engn Jais 229305 Uttar Pradesh India Kyoto Univ Adv Sci Nagamori Actuator Res Ctr Kyoto 6158577 Japan

Power electronic converters are used for an efficient and controlled conversion of power generated from renewable energy sources and can interface generated power to the grid. Among available power converters, voltage source inverters (VSIs) have been widely employed for grid-connected applications due to better controllability with higher efficiency. Although various conventional, as well as modern control techniques, have been developed for grid connected VSI system, there is a need to select suitable control technique based on application and control requirements. Hardware-in-the-loop (HIL) is considered as a realistic approach for the development of system and control due to the inclusion of an actual hardware system. In this paper, a HIL approach is adopted for the comprehensive analysis and development of a grid connected VSI system using a field programmable gate array (FPGA). The control techniques must deal with trade-off, based on the features and limitations. Therefore, a grid-connected VSI system is developed considering employment of two different conventional control techniques: hysteresis current control (HCC) and PI-based space vector modulation (PI-SVM), as well as finite state model predictive control (FS-MPC) as a modern control technique for investigation considering different parameters. All three control systems are developed through a digital simulator of Xilinx that is integrated with MATLAB-Simulink, while considering an FPGA based system development and testing through FPGA HIL co-simulation methodology.

关键词： field-programmable gate array finite state model predictive control grid-connected system hardware-in-the-loop hysteresis current control space vector modulation voltage source inverter

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High-performance computer system dedicated to ray-wavefront conversion technique aimed to display holograms in real-time

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OPTICAL ENGINEERING 2023年第8期62卷 085102-085102页

作者： Maruyama, Tatsuya Ichihashi, Yasuyuki Hoshi, Ikuo Kakue, Takashi Shimobaba, Tomoyoshi Ito, Tomoyoshi Chiba Univ Grad Sch Engn Chiba Japan Natl Inst Informat & Commun Technol Radio Res Inst Koganei Japan

Holography is the ultimate three-dimensional (3D) imaging technology, and research is actively being conducted on generating at high-speed holograms with enormous amounts of information and improving image quality. Because computer holography is based on wave optics algorithms, reconstructing the texture of 3D images is difficult. On the other hand, in principle, reconstructing texture in integral photography based on geometric optics is easy and the method is well established. We developed a high-performance special-purpose computer, called holographic reconstruction for ultra-realistic imaging, dedicated to the ray-wavefront conversion method. The design and implementation of the circuit for the hologram generation were performed using field-programmable gate array technology. Parallelization was performed at each step for increasing the speed of the calculation process. Furthermore, by sending output data directly to a displaying device in the high-definition multimedia interface, the communication between the host personal computer (PC) and special-purpose computer was controlled in one direction, which significantly reduced communication time. The system was similar to 7.7 times faster than a PC alone and succeeded in the holographic reproduction of a textured 3D image in real time at 30 frames per second for a 1024 x 1024-pixel hologram. (c) The Authors. Published by SPIE under a Creative Commons Attribution 4.0 International License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

关键词： holography computer-generated hologram field-programmable gate array light-ray information discrete Fourier transform

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Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

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JOURNAL OF ELECTRONIC IMAGING 2023年第1期32卷 013012-013012页

作者： Singh, Pulkit Agrawal, Bhaskar Chaurasiya, Rahul Kumar Acharya, Bibhudendra Natl Inst Technol Raipur Dept Elect & Commun Engn Raipur Chhattisgarh India Maulana Azad Natl Inst Technol Bhopal Dept Elect & Commun Engn Bhopal Madhya Pradesh India

Internet of Things (IoT) connects a wide range of small devices over a large network, allowing for a wide range of applications. With the advancement of open-source public networks (such as IoT), image transmission for resource-constrained devices is becoming more insecure. In this paper, two hardware implementations for KLEIN block cipher are proposed that can provide security to encrypt different sets of images under resource-constrained applications (such as wireless sensor network, radio frequency identification, IoT etc.). An improvement in maximum operating frequency of 32.72% and 75.66% in the proposed serial and pipelined architectures is observed compared with the state-of-the-art design, respectively. The implemented pipelined architecture yields high throughput of 1840.15 MHz, and the serialized architecture implies 108 numbers of slices implemented on field-programmable gate array (FPGA) xc5vlx50t-3ff1136 device. On application-specific integrated circuit (ASIC) platform, the proposed serialized KLEIN implementation consumed less area in terms of gate equivalent. The existing solution was also subjected to changing correlation coefficients, number of pixels changing rate, unified average changing intensity, and entropy values. The simulation results validate the effectiveness of the performance of the proposed encryption scheme.

关键词： security lightweight cryptography field-programmable gate array application-specific integrated circuit image encryption

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Real-time post-processing for physical-layer secure key distribution in fiber networks

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OPTICS COMMUNICATIONS 2023年 529卷

作者： Cao, Ying Zhang, Liuming Huang, Xinran Hu, Weisheng Yang, Xuelin Shanghai Jiao Tong Univ Key Lab Adv Opt Commun Syst & Nerworks Shanghai 200240 Peoples R China

Physical-layer secure key distribution (PLSKD) in fiber networks provides robust security and full compatibility with current fiber infrastructure. The post-processing is generally required to improve the key consistency, security, and randomness in PLSKD. However, offline digital signal processing was generally adopted in the previous PLSKD schemes, while the real-time high-speed post-processing is necessary towards the practical PLSKD applications. In this paper, a real-time pipeline post-processing is designed and demonstrated using field-programmable gate array (FPGA) boards. A complete set of post-processing is applied, including double -threshold quantization, information reconciliation (IR) with Bose-Chaudhuri-Hocquenghem code, and privacy amplification (PA) with SM3 hash algorithm. The system architecture is detailed by combining all these processing steps, where the trade-offs for the post-processing scheme are analyzed. We also assess the performance of post-processing implementation on FPGA in terms of throughput and hardware resource utilization. The throughput of post-processing is optimized by pipeline design approach with the parallel processing capability of FPGA, where the maximum data throughputs are 50, 57.1, and 332.5 Mb/s for the quantization, IR, and PA, respectively. On the FPGA platform, the final key rate is up to 12.2 Mb/s. The proposed real-time post-processing FPGA prototype is a good candidate for the practical application of PLSKD in fiber networks.

关键词： Secure key distribution Post-processing Quantization Information reconciliation Privacy amplification field-programmable gate array

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FPGA-Based Hierarchical Configuration Method for Conservation-Oriented Ecological Garden Landscape for a Smart City Development

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JOURNAL OF TESTING AND EVALUATION 2023年第3期51卷 1555-1570页

作者： Yu, Jia Yang, Rui Shenyang Univ Coll Life Sci & Bioengn Shenyang 110044 Peoples R China Shenyang Vanke Real Estate Dev Co Ltd Design Dept Shenyang 110044 Peoples R China

More and more attention is paid to development and conservation at home. In response to national policies, this paper proposes a field-programmable gate array (FPGA)-based hierar-chical configuration method for conservation-oriented ecological garden landscape to build sustainable ecological garden landscapes. Following the principles of uniformity, adapting measures to local conditions, and aesthetics in hierarchical configuration of conservation -oriented ecological garden landscape, this paper gives comprehensive consideration to exami-nation factors and landscape plant rationality in hierarchical configuration and takes scenic beauty estimates to evaluate the plant landscape configuration effect. Under the guidance of hierarchical configuration principles and evaluation indicators for conservation-oriented ecological garden landscape, this paper adopts the FPGA partition algorithm to design the hierarchical conservation design model of the garden landscape. In the subsequent hierarchical configuration of ecological garden landscape, the lowest energy consumption is maintained, plant communities are reasonably collocated to achieve hierarchical configuration of the gar-den landscape, and energy consumption in the landscape is reduced through measures such as material and water conservation, thus achieving hierarchical configuration of conservation -oriented ecological garden landscape. Experimental research results of a forest park in Quanzhou conclude that this method can achieve hierarchical configuration of the ecological garden landscape in the forest park. Plant collocation is reasonable in the more aesthetic and concise landscape configuration. At the same time, the configuration process saves water re-sources and reduces energy consumption, demonstrating the advantage of low configuration costs.

关键词： field-programmable gate array conservation-oriented ecology garden landscape hierarchical configuration

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Multi-precision binary multiplier architecture for multi-precision floating-point multiplication

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IET CIRCUITS DEVICES & SYSTEMS 2021年第5期15卷 455-464页

作者： Tomar, Geetam Singh George, Marcus Llyode Tomar, Abhineet Singh Rajkiya Engn Coll Sonbhadra India Univ West Indies Dept Elect & Comp Engn St Augustine Trinidad Tobago Volvo Grp Trucks Technol Gothenburg Sweden

Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating-point multiplication is an important component. The dynamic range of numbers represented by floating-point arithmetic is very large compared with that of fixed-point numbers of the same bit width. A mantissa similarity investigator (MSI)-interfaced multi-precision binary multiplier architecture is developed and can be used in data-intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single-, double-, quadruple- and octuple-precision modes for mantissa multiplication according to the IEEE 754 standard for floating-point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field-programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator.

关键词： data-intensive applications video processing multiplication operation fixed-point numbers arithmetic operations arithmetic logic units double-precision modes octuple-precision modes mantissa multiplication image processing engineering applications single-precision modes field-programmable gate array floating-point numbers mantissa similarity investigator interfaced multiprecision binary multiplier architecture multiprecision floating-point multiplication IEEE 754 standard logic design floating point arithmetic ALU logical operations field programmable gate arrays Xilinx ISE Design Suite 14.7 floating-point arithmetic signal processing multiplying circuits quadruple-precision modes ISim simulator core components variable precision

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