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FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第9期32卷 1684-1695页

作者： Coulon, Samuel Bao, Tianyou Xie, Jiafeng Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA

The extended greatest common divisor (XGCD)computation is a critical component in various cryptographic applications and algorithms, including both pre- and postquantum cryptosystems. In addition to computing the greatest common divisor (GCD) of two integers, the XGCD also produces Be z out coefficients b(a )and b(b) which satisfy GCD(a, b) = a x b(a )+ b x b(b). In particular, computing the XGCD for large integers is of significant interest. Most recently, XGCD computation between 6479-bit integers is required for solving Nth-degree truncated polynomial ring unit (NTRU) trapdoors in FALCON, a National Institute of Standards and Technology (NIST)-selected postquantum digital signature scheme. To this point, existing literature has primarily focused on exploring software-based implementations for XGCD. The few existing high-performance hardware architectures require significant hardware resources and may not be desirable for practical usage, and the lightweight architectures suffer from poor performance. To fill the research gap, this work proposes a novel FPGA-based scalable and lightweight accelerator for large integer XGCD (FELIX). First, a new algorithm suitable for scalable and lightweight computation of XGCD is proposed. Next, a hardware accelerator (FELIX)is presented, including both constant- and variable-time versions. Finally, a thorough evaluation is carried out to showcase the efficiency of the proposed FELIX. In certain configurations, FELIX involves 81% less equivalent area-time product (eATP)than the state-of-the-art design for 1024-bit integers, and achieves a 95% reduction in latency over the software for 6479-bit integers(FALCON parameter set) with reasonable resource usage. Overall, the proposed FELIX is highly efficient, scalable, lightweight, and suitable for very large integer computation, making it the first such XGCD accelerator in the literature (to the best of our knowledge).

关键词： Software algorithms Polynomials Software field programmable gate arrays Cryptography Computer architecture Hardware acceleration Cryptographic applications field-programmable gate array hardware accelerator large integer extended greatest common divisor (GCD)

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Profile generation using the filtering technique for the fast motion and smooth performance in the hardware level of autonomous system

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2023年第8期17卷 330-350页

作者： Lam, Duc Khai Ngo, Nhat Minh Ngo, Ha Quang Thinh Univ Informat Technol Comp Engn Dept Ho Chi Minh City Vietnam Ho Chi Minh City Univ Technol HCMUT Fac Mech Engn Dept Mechatron Ho Chi Minh City Vietnam Vietnam Natl Univ Ho Chi Minh City VNU HCM Ho Chi Minh City Vietnam Ho Chi Minh City Univ Technol HCMUT 268 Ly Thuong KietDist 10 Ho Chi Minh Vietnam

This study addresses the challenge of motion control in autonomousvehicles through the introduction of a novel profile generation design. Specifically,autonomous vehicles often contend with uncertain factors and physicallimitations within their operational environments, such as abrupt changes inacceleration or intricate parametric motion profiles. To tackle this problem, afiltering technique for motion profile generation is proposed, leveraging ahardware programming language as its foundation. The investigation begins byanalyzing the specific structure of the mobile platform, which includes twoactive side wheels, two passive rear wheels, a high load capacity, and adifferential drive mode. Building upon this theoretical basis, the proposedfiltering technique is introduced to attain smooth motion profiles and optimizetiming. Furthermore, the study suggests the use of FPGA (field programmablegate array) acceleration to expedite these computations for swift motionprocessing. To validate the efficacy of the proposed method, both the mobilevehicle and the load are simulated as a one-axis linear ball-screw system withan aluminum ruler. The experimental results unequivocally demonstrate theeffectiveness, feasibility, and applicability of the proposed approach across avariety of industrial solutions. The filtering technique to generatemotion profile based on the hardware programming language is introduced. First,the specific structure of mobile platform involves two active side wheels andtwo passive rear wheels. Second, theoretical control using the polynomialfunction is mentioned to provide the concrete basis. Third, field programmablegate array-accelerated approach is additionally implemented thesecomputations for rapid ***

关键词： autonomous vehicle digital signal processing field-programmable gate array filtering technique motion planning

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Modelling and control of dual input boost converter with voltage multiplier cell

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IET CIRCUITS DEVICES & SYSTEMS 2019年第8期13卷 1267-1276页

作者： Appikonda, Mohan Kaliaperumal, Dhanalakshmi Natl Inst Technol Dept Elect & Elect Engn Tiruchirappalli 620015 Tamil Nadu India Natl Inst Technol Dept Instrumentat & Control Engn Tiruchirappalli 620015 Tamil Nadu India

A dual input DC-DC converter with dual boost and integrated voltage multiplier cell operating at duty cycles larger than 0.5 is a necessity to achieve a high voltage gain for energy systems possessing two independent renewable energy resources. Output voltage regulation during load changes and input disturbances is the requisite of an energy system, which is achieved by the implementation of a suitable control action, which further requires the dynamic model of the converter. The modelling of this higher order converter with overlapping switching signals is complicated. The small-signal transfer function model based on state-space averaging followed by small-signal linearisation is verified using MATLAB and powersim (PSIM). The output voltage to duty cycle transfer functions significantly contributes to representing the converter dynamics from which its right-half s-plane zero is analysed. Since it is a non-minimum phase system, a dual loop control strategy is adopted. Voltage regulation and active current sharing are ensured from the simulation and experimental responses of the uncompensated and compensated systems. Further, from the derived integer-order converter model a fractional controller is designed and its dynamic response is compared with the traditional controller. A 200 W prototype of the converter is developed, and the control is implemented using field-programmable gate array.

关键词： field programmable gate arrays transfer functions DC-DC power convertors voltage control voltage regulators voltage multipliers dynamic response renewable energy sources linearisation techniques load changes input disturbances energy system dynamic model higher order converter overlapping switching signals small-signal transfer function model state-space averaging small-signal linearisation duty cycle transfer functions converter dynamics nonminimum phase system dual loop control strategy uncompensated systems fractional controller dynamic response dual input boost converter dual input DC-DC converter dual boost integrated voltage multiplier cell duty cycles voltage gain independent renewable energy resources output voltage regulation integer-order converter model field-programmable gate array power 200 0 W

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Radiation Environment-Constrained FPGA Reinforcement Technology and Reliability Research Utilizing Error Control Coding

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IEEE ACCESS 2024年 12卷 74737-74750页

作者： Zhang, Dongliang Wu, Wenchen Shanghai Univ Elect Power Coll Automat Engn Shanghai 200090 Peoples R China Shanghai Key Lab Power Stn Automat Technol Shanghai 200090 Peoples R China

In the radiation work environment of nuclear power plants and similar facilities, radiation can induce Single Event Upsets (SEUs) and even Multiple Bit Upsets (MBUs) in field-programmable gate arrays (FPGAs) and related devices. The hardware reinforcement techniques for FPGAs have strict material requirements and high costs, making implementation challenging. In contrast, FPGA software reinforcement techniques utilize error control coding to strengthen FPGA memory and combine with FPGA dynamic reconfiguration technology to reinforce the encoding and decoding modules. In this study, a BRAM fault injection experimental system is designed using Vivado to compare the reinforcement measures such as Hamming code, interleaved Hamming code, interleaved cyclic code, BCH code, and triple modular redundancy. Mathematical methods are employed to calculate their reliability performance indicators. The conclusion is that BCH (31,16,3) code exhibits the highest reliability, consumes the most resources, and can correct all errors of three bits or fewer. On the other hand, matrix interleaved code (28,16) can address the majority of MBUs, correcting all burst errors of four bits or fewer and some sporadic errors while utilizing relatively fewer resources.

关键词： Codes field programmable gate arrays Encoding Decoding Polynomials Random access memory Power generation Reliability field-programmable gate array error control coding interleaving BCH code reliability

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An efficient FPGA technology mapping tightly coupled with logic minimization

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1997年第10期E80A卷 1807-1812页

作者： Yi, K Ohm, SY Jhon, CS Department of Computer Engineering Seoul National University South Korea Department of Computer Science Seoul Women's University South Korea Research Institute of Advanced Computer Technology Seoul National University South Korea

The FPGA logic synthesis consists of logic minimization step and technology mapping step. These two steps are usually performed separately to reduce the complexity of the problem. Conventional logic minimization methods try to minimize the number of literals of a given Boolean network, while FPGA technology mapping techniques attempt to minimize the number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture specific feature. Therefore, most of the existing technology mapping systems take into account reorganization of its input circuits to get better mapping results. Such a loosely coupled logic synthesis paradigm may cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system takes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Boolean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optimality and supports versatile cost functions. In addition, a fast and exact library management technique is devised for efficient FPGA cell matching which is one of the most frequently used operations in the FPGA logic synthesis. To demonstrate the efficiency of our approach, we applied our system to MCNC benchmarks and compared the results with those of the existing systems. The experimental results show that our approach is better than any of the existing systems in terms of area and delay.

关键词： logic synthesis technology mapping logic minimization Boolean network field-programmable gate array

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FPGA-Based Hardware Design for Scale-Invariant Feature Transform

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IEEE ACCESS 2018年 6卷 43850-43864页

作者： Li, Shih-An Wang, Wei-Yen Pan, Wei-Zheng Hsu, Chen-Chien James Lu, Cheng-Kai Tamkang Univ Dept Elect Engn New Taipei 25137 Taiwan Natl Taiwan Normal Univ Dept Elect Engn Taipei 10610 Taiwan Univ Teknol PETRONAS Dept Elect & Elect Engn Bandar Seri Iskandar 32610 Malaysia

This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the computing costs, Gaussian kernels are calculated offline for use in Gaussian filters. To eliminate low-contrast points, the inverse of a Hessian matrix is required for hardware implementation, which results in poor performance because dividers are needed. To solve this problem, this paper presents a new mathematical derivation model to implement the low-contrast detection, avoiding the use of any dividers. For the implementation of the normalization module, a large number of dividers are required by traditional methods, which adversely affects the computational efficiency. This paper presents a new architecture using only one divider to implement the normalization function in hardware. Thanks to the parallel processing architecture proposed to design the image pyramid, SIFT detection, and SIFT descriptor, the computational efficiency of the SIFT algorithm is significantly improved. As a result of the proposed design method, the requirement of logic elements in the FPGA hardware is greatly reduced and system frequency is significantly increased. Experimental results show that the proposed hardware architecture outperforms existing techniques in terms of resource usage and computational efficiency for real-time image processing.

关键词： Scale-invariant feature transform field-programmable gate array parallel processing architecture

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Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第2期26卷 919-935页

作者： Ayat, Sayed Omid Khalil-Hani, Mohamed Ab Rahman, Ab Al-Hadi Univ Teknol Malaysia Fac Elect Engn VeCAD Res Lab Skudai Johor Malaysia

In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its flexibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Roofline model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

关键词： Convolutional neural network field-programmable gate array energy efficiency Roofline model race-to-halt strategy

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A fast method for particle tracking and triggering using small-radius silicon detectors

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2020年第0期957卷 163427-000页

作者： Kotwal, Ashutosh V. Duke Univ Dept Phys Durham NC 27708 USA

We propose an algorithm, deployable on a highly-parallelized graph computing architecture, to perform rapid reconstruction of charged-particle trajectories in the high energy collisions at the Large Hadron Collider and future colliders. We use software emulation to show that the algorithm can achieve an efficiency in excess of 99.95% for reconstruction with good accuracy. The algorithm can be implemented on silicon-based integrated circuits using field-programmable gate array technology. Our approach can enable a fast trigger for massive charged particles that decay invisibly in the tracking volume, as in some new-physics scenarios related to particulate dark matter. If production of dark matter or other new neutral particles is mediated by metastable charged particles and is not associated with other triggerable energy deposition in the detectors, our method would be useful for triggering on the charged mediators using the small-radius silicon detectors.

关键词： Charged particle tracking Track trigger Unsupervised machine learning field-programmable gate array Electronics

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Simple and robust self-healing technique for millimetre-wave amplifiers

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IET CIRCUITS DEVICES & SYSTEMS 2016年第1期10卷 37-43页

作者： Jia, Haikun Chi, Baoyong Kuang, Lixue Wang, Zhihua Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

A simple and robust self-healing technique for millimetre-wave (mm-wave) amplifiers is proposed. The self-healing technique can correct the operation frequency shifting of the amplifier (including its input and output impedance matching shifting) due to process, voltage, and temperature variations and modelling inaccuracy. A mm-wave amplifier with digitally controlled artificial dielectric transmission lines as fine frequency tuning components and an on-chip power detector as the frequency shifting detector has been implemented in 65 nm complementary metal-oxide-semiconductor to verify the effectiveness of the technique. The operating frequency of five amplifier chips is calibrated by running the self-healing algorithm on a field-programmable gate array development board. On average, the gain of the amplifier is improved by 2.60 dB from 13.66 to 16.26 dB and the input matching is improved by 12.78 dB from -4.89 to -17.67 dB at 56 GHz after the proposed self-healing procedure.

关键词： digitally controlled artificial dielectric transmission line on-chip power detector dielectric materials self-healing technique operation frequency shifting complementary metal-oxide-semiconductor gain 13.66 dB to 16.26 dB mm-wave amplifier frequency tuning component millimetre-wave amplifier impedance matching field-programmable gate array circuit tuning transmission lines size 65 nm digital control impedance matching shifting temperature variation gain 2.6 dB CMOS integrated circuits field programmable gate arrays frequency shifting detector frequency 56 GHz amplifier chip millimetre wave amplifiers

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FPGA Acceleration for 3-D Low-Dose Tomographic Reconstruction

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2021年第4期40卷 666-679页

作者： Zhang, Wentai Qiao, Linjun Hsu, William Cui, Yong Jiang, Ming Luo, Guojie Peking Univ Ctr Energy Efficient Comp & Applicat Beijing 100871 Peoples R China Peking Univ Sch Math Sci Dept Informat Sci Beijing 100871 Peoples R China Univ Calif Los Angeles Dept Radiol Sci Los Angeles CA 90095 USA Peking Univ Canc Hosp & Inst Minist Educ Dept Radiol Key Lab Carcinogenesis & Translat Res Beijing 100142 Peoples R China

X-ray computed tomography (CT) is commonly used to obtain vivo images to characterize diseases but results in radiation exposure to patients. Low-dose CT (LDCT) provides CT images of clinical quality with reduced cumulative radiation dose. Iterative image reconstruction methods with effective regularization are used for LDCT but generally require more computing resources and induce higher computational load than the conventional filtered backprojection (FBP) methods. The high computational demand of the iterative reconstruction (IR) with notably increased reconstruction time precludes its routine clinical application. In this work, we focus on the FPGA acceleration of a compute-intensive full IR (full-IR) algorithm based on the Mumford-Shah regularization. At the algorithmic level, we propose a beam-based asynchronous update algorithm to reduce the computational cost and alleviate the conflicts. At the hardware-level, we first present pipeline-friendly optimization for the original algorithm to increase the computation throughput. We then apply the LDCT-specific tiling strategy to improve the data reuse rate. The experimental results show that our implementation takes 8.5 min to reconstruct a typical physical phantom with the image quality comparable with the vendor's result. The FPGA implementation achieves 11.6x throughput against the state-of-the-art GPU version.

关键词： Asynchronous parallelism field-programmable gate array iterative image reconstruction low-dose computed tomography (CT)

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