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检索条件"主题词=field-programmable gate array"

共 571 条记录，以下是181-190 订阅

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A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once-Write Shifting 14

A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile...

引用

14th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSoC)

作者： Suzuki, Daisuke Oka, Takahiro Hanyu, Takahiro Univ Aizu Sch Comp Sci & Engn Aizu Wakamatsu Japan Tohoku Univ Grad Sch Engn Sendai Miyagi Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi Japan

ISBN: (纸本)9781665438605

A binary convolutional neural network (BCNN) accelerator using a nonvolatile field-programmable gate array (NV-FPGA) with only-once-write shifting is presented. During the basic operation of the BCNN, the feature maps and weights are read from the block RAM (BRAM) and serially transferred to processing elements. The use of only-once-write shifting makes it possible to greatly reduce write power consumption such serial data transfer in the NV-FPGA. Meanwhile, since the BCNN computing is composed of the nested loop, the memory access potentially has a temporal locality. This means that once the data is read from the BRAM, it can be reused among several layers. By focusing this feature and performing loop interchange, the number of memory access can be minimized and the idle time is maximized. If the BRAM is nonvolatile, wasted standby energy consumption during idle state is completely eliminated by the use of power gating technique. As a result, the proposed BCNN accelerator is 66.5% lower energy consumption than a conventional volatile-FPGA-based BCNN accelerator in typical digit recognition task with MNIST dataset.

关键词： Binary convolutional neural network field-programmable gate array Nonvolatile Edge-AI accelerator Magnetic tunnel junction Low power

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FPGA-based UART Transmission for VGA Image Display 23

FPGA-based UART Transmission for VGA Image Display

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Proceedings of the 2023 International Conference on Advances in Artificial Intelligence and Applications

作者： Rongbiao Xiang Jianmin Wang Boxin Chen Pin Lyu School of Electronic and Information Engineering Ningbo University of Technology China

ISBN: (纸本)9798400708268

In the increased demand for video display of embedded small and medium-sized devices, the design uses a universal asynchronous receiver/transceiver UART for data transmission and VGA for image display through a standard video interface. The serial communication based on field programmable gate array FPGA is implemented to control the image display of video graphics array VGA, and the top-level module of VGA display is divided downward based on the modularity idea, and the hardware description language is used to realize the establishment of each functional module circuit. The logic function simulation is carried out by ModelSim simulation software, and the final board-level verification is realized by DE2-115.

关键词： field-programmable gate array Universal Asynchronous Receiver/Transceiver VGA Image Display

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Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Controller Design with Resistive Random-Access Memories (RRAM) for field-programmable gate arrays (FPGA)

Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Cont...

引用

IEEE Regional Symposium on Micro and Nanoelectronics (IEEE-RSM)

作者： Chee, Hock Leong Kumar, T. Nandha Almurib, Haider A. F. Kang, Desmond Wen Hui Univ Nottingham Dept Elect & Elect Engn Semenyih Selangor Malaysia

ISBN: (纸本)9781728104607

This paper studies the simulation results of a novel controller circuit design for non-volatile (NV) look-up tables (LUT) combined with an electrical model of a resistive random-access memory (RRAM)-an emerging non-volatile memory (NVM) device. The Write and Read schemes of the controller is tested for a 2x2 RRAM array. The selected RRAM successfully switches between low '0' and high '1' while the unselected the RRAM remain undisturbed, demonstrating the elimination of the intrinsic sneak-path current problem in RRAMs. Reading of a selected RRAM is also performed with agreeable results.

关键词： field-programmable gate array memristor non-volatile look-up table non-volatile memory resistive random-access memory resistive switching

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A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime 24

A Hardware/Software Concept for Partial Logic Updates of Emb...

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24th Euromicro Conference on Digital System Design (DSD)

作者： Scheipel, Tobias Brungs, Peter Baunach, Marcel Graz Univ Technol Inst Tech Informat Graz Austria Univ Wurzburg Chair Comp Sci 5 Wurzburg Germany

ISBN: (纸本)9781665427036

Embedded systems are built from various hardware components and execute software on one or more microcontroller units (MCU). These MCUs usually contain a fixed integrated circuit, thus disallowing modifications to their logic at runtime. While this keeps the instruction set architecture (ISA) fixed as well, it leaves the software as the only flexible part in the system. But what if the MCU logic could be easily changed at runtime in order to fix bugs or if the ISA could be extended on-the-fly in order to introduce application-specific instructions and features on demand? This work demonstrates a concept for introducing more hardware flexibility through application-specific MCU modifications. Therefore, the MCU is implemented as a soft core on a field-programmable gate array (FPGA) and we reconfigure its logic with support of the operating system (OS) running on it. The reconfiguration happens on-the-fly, so no interruption of the application code or even a system restart is required. Therefore, (i) the MCU pipeline is specially designed for extensibility by new instructions, and (ii) the FPGA is selected to support partial self-reconfiguration of its logic cells at runtime. As long as an instruction is not yet part of the ISA, the OS supports its emulation to provide a consistent interface for applications. Apart, no special compiler support is required, but the application must provide either the emulation code or a hardware description for adding the required logic. For a proof of concept, we use a RISC-V based MCU on a Xilinx Artix-7 FPGA and for evaluating the general benefit of our approach we use an algorithm that is costly when executed with the original ISA but fast with application-specific instructions added at runtime. The experimental evaluation also shows that the on-the-fly hardware update does not disrupt or compromise the software execution flow.

关键词： partial reconfiguration embedded systems reconfigurable logic field-programmable gate array processor architecture operating system hardware software co-design

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Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks 23

Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural ...

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Proceedings of the 2023 ACM/SIGDA International Symposium on field programmable gate arrays

作者： Ruiqi Chen Haoyang Zhang Yuhanxiao Ma Enhao Tang Shun Li Yanxiang Zhu Jun Yu Kun Wang Fudan University Shanghai China New York University New York NY USA Fuzhou University Fuzhou China VeriMake Innovation Lab Nanjing China

ISBN: (纸本)9781450394178

Graph Neural Networks (GNNs) have outstanding performance on graph-structured data and have been extensively accelerated by field-programmable gate array (FPGA) in various ways. However, existing accelerators significantly lack flexibility, especially in the following two aspects: 1) Many FPGA-based accelerators only support one GNN model. 2) The processes of re-synthesizing and bitstream re-generating are very time-consuming for new GNN models. To this end, we propose a highly integrated FPGA-based overlay processor for general GNN accelerations named Graph-OPU. Regarding the data structure and operation irregularity, we customize the instruction sets to support irregular operation patterns in the inference process of GNN models. Then, we customize our datapath and optimize the data format in the microarchitecture to take full advantage of high bandwidth memory (HBM). Moreover, we design the computation module to ensure a unified and fully-pipelined process of sparse matrix multiplication (SpMM) and general matrix multiplication (GEMM). Users can avoid the process of FPGA reconfiguration or RTL regeneration for the newly invented GNN models. We implement the hardware prototype on Xilinx Alveo U50 and test the mainstream GNN models with 9 datasets. Graph-OPU can achieve an average of 435× and 18× speedup, while 2013× and 109× better energy efficiency, compared with the Intel I7-12700KF processor and NVIDIA RTX3090 GPU, respectively. To the best of our knowledge, Graph-OPU is the first in-depth study on FPGA-based general processors for GNN acceleration with high speedup and energy efficiency.

关键词： high bandwidth memory graph neural network field-programmable gate array overlay processor

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A Hardware-oriented Algorithm of GMM-MRCoHOG for High-performance Human Detection by an FPGA

A Hardware-oriented Algorithm of GMM-MRCoHOG for High-perfor...

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International Workshop on Advanced Imaging Technology (IWAIT)

作者： Nagamine, Yuya Yoshihiro, Kazuki Shibata, Masatoshi Yamada, Hideo Enokida, Shuichi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Fukuoka Japan EQUOS Res Co Ltd Tokyo Japan Kyushu Inst Technol Grad Sch Comp Sci & Syst Engn Fukuoka Japan

ISBN: (数字)9781510643659

ISBN: (纸本)9781510643659

In this study, we propose a hardware-oriented Gaussian mixture model - multiresolution co-occurrence histograms of oriented gradients (GMM-MRCoHOG) algorithm for efficient human detection by a field-programmable gate array (FPGA). GMM- MRCoHOG is a HOG-based human detection method in which the computation of angles is quantized to 36 directions and 2D Gaussian distribution computation causes a decrease in processing speed and an increase in hardware resource usage. We propose a hardware-oriented algorithm to solve these problems. First, we propose a rough angle computation method of comparison with a tangent table. Second, we propose a bit-shifting-based Gaussian distribution computation method. Experimental results show that the proposed hardware-oriented algorithm does not significantly reduce the detection accuracy of GMM-MRCoHOG. High-level synthesis results of the FPGA implementation show that fast, low-resource processing is possible.

关键词： Image processing Human detection Histograms of oriented gradients Gaussian mixture model Hardware-oriented algorithm field-programmable gate array

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Analysis of the programmable Soft IP-cores Implementation for FPGAs

Analysis of the Programmable Soft IP-cores Implementation fo...

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

作者： Khvatov, Vasilii M. Zheleznikov, Daniil A. Gavrilov, Sergey, V Russian Acad Sci IPPMRAS Inst Design Problems Microelect Moscow Russia

ISBN: (纸本)9781665404761

Soft programmable IP-cores are usually used to speed up the integrated circuits design in FPGA. Soft blocks are formed from programmable logical FPGA elements independently from specific location on the FPGA and do not have pre-routed paths. Some FPGA architectures contain specialized resources to improve IP-cores design efficiency. It is necessary to consider these resources in CAD methods and components development. The paper presents the comparative analysis of two types of soft IP-cores implementation. The first type utilizes the architectural features of the FPGA due to a special block library. The second one obtains the results of automatic synthesis in a standard elements basis. The final size of designed IP-cores and the amount of utilized routing resources are compared. Also, the paper describes the specifics of the FPGA routing resources usage and the other implementation issues of such soft IP-cores as an n-bit adder / subtractor, an up-to-N counter, and a shift register.

关键词： IP-cores Computer Aided Design CAD field-programmable gate array FPGA Design Flow Routing

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Performance Study of Multi-tenant Cloud FPGAs

Performance Study of Multi-tenant Cloud FPGAs

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35th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Mbongue, Joel Mandebi Saha, Sujan Kumar Bobda, Christophe Univ Florida ECE Dept Gainesville FL 32611 USA

ISBN: (纸本)9781665435772

Cloud deployments now increasingly provision FPGA accelerators as part of virtual instances. While commercial clouds still essentially expose single-tenant FPGAs to the users, the growing demand for hardware acceleration raises the need for architectures supporting FPGA multi-tenancy. In this work, we explore the trade-off between hardware consolidation and performance. Experiments show that FPGA multi-tenancy increases hardware utilization and decreases IO performance in the order of microseconds compared to the single-tenant model. The experiments also demonstrate that implementing on-chip communication between the hardware workloads of a cloud user significantly reduces the overall communication overhead.

关键词： Cloud field-programmable gate array Multi-tenancy

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Improving Pathfinder Algorithm Perfomance for FPGA Routing

Improving Pathfinder Algorithm Perfomance for FPGA Routing

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

作者： Zapletina, Mariya A. Zheleznikov, Daniil A. Gavrilov, Sergey, V RAS Inst Design Problems Microelect Zelenograd Russia

ISBN: (纸本)9781665404761

The paper presents some algorithmic improvements to accelerate the routing stage for FPGA. One of the main advantages of FPGA is the high development speed;thereby the importance of efficient computer-aided design tools for modern FPGA is hard to overestimate. The placement and routing stages are crucial for the FPGA performance, and meanwhile they take up a significant part of the design time. The investigated base routing algorithm is the modified Pathfinder for the mixed routing resources graph. Pathfinder is a popular iterative negotiation-based router acting on the principle of eliminating nets congestions. Due to the proposed algorithmic improvements, such as ignoring the uncongested nets while ripup and rerouting stage, and some other, the summary routing time is reduced significantly. The observed average time decrease is from 1.3X to 2.6X depending on the FPGA architecture. The benchmarks ISCAS'85&89, LGSynth'89 and several real industrial circuits were used for testing.

关键词： field-programmable gate array congestion-aware routing routing acceleration Pathfinder modification shortest path search

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A Long-Range Hardware Bubble Corrector Technique for Short-Pulse-Width and Multiple-Registration Encoders 7

A Long-Range Hardware Bubble Corrector Technique for Short-P...

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7th International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP)

作者： Tancock, Scott Rarity, John Dahnoun, Naim Univ Bristol Dept Elect & Elect Engn Bristol Avon England

ISBN: (纸本)9781665436977

Bubble detection and correction logic is vital in modern data capture devices to solve bubbles in the output thermometer codes due to non-linearities in the scale causing negative bin widths. Previous bubble correction techniques are either unsuitable for short pulse widths and multiple registration (ones-encoder) or have a very short range (all other methods). In this paper, we propose a hardware technique to detect and correct bubbles up to the length of the pulse width while preserving position information using a hybrid between the ones-encoder and a single stage of a modified insertion sort. This design was shown to meet timing on a Xilinx Artix-7 FPGA at 100 MHz or above using only 13% of the device, demonstrating hardware-viability. The design is also fully-pipelined to demonstrate high bandwidths. The limitations of the algorithm are stated and some possible improvements are suggested.

关键词： Hardware field-programmable gate array Bubble Correction Converters Encoders Thermometer Code Population Counter

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