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An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec

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TRANSACTIONS OF THE INSTITUTE OF MEASUREMENT AND CONTROL 2021年第16期43卷 3672-3685页

作者： Balamurugan, S. M. Seshasayanan, R. Anna Univ Dept Elect & Commun Engn Chennai 600025 Tamil Nadu India

Motion estimation and motion compensation techniques are effectively used for removing temporal redundancy between adjacent frames during video compression, but video quality will be degraded with the traditional pixel-based matching algorithms. To overcome this issue, diamond adaptive rood pattern search algorithm-based block-matching motion estimation algorithms are proposed in this manuscript for multi-stranded codec hardware design, which provide a high compression rate with less computational complexity. In this work, a diamond adaptive rood pattern search algorithm is used, which is a combination of a diamond-search algorithm and adaptive rood pattern search. In addition, the proposed algorithm applies multiple search strategies and terminates unnecessary searching while reserving high data regularity. The proposed diamond adaptive rood pattern search algorithm-based block-matching motion estimation algorithm for multi-stranded codec hardware design provides good performance in terms of complex calculations reduction and reaches a high speed in comparison to traditional search algorithms. The proposed architecture is implemented in Xilinx ISE design 14.5 suite and the implemented results are compared to the existing motion estimation techniques on field-programmable gate array devices. Simulation results shows that the diamond adaptive rood pattern search algorithm for multi-stranded codec hardware design provides a very good improvement in terms of computations overhead reduction, with 96.4%, 97.3% latency and 98.7% throughput and achieves a high compression rate without video quality degradation.

关键词： Motion estimation block-based matching algorithms (BMAs) field-programmable gate array adaptive rood pattern search (ARPS) diamond search algorithm

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A field-programmable gate array system for sonar image recognition based on convolutional neural network

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2021年第10期235卷 1808-1818页

作者： Wang, Chong Jiang, Yu Wang, Kai Wei, Fenglin Jilin Univ Coll Comp Sci & Technol Changchun 130012 Peoples R China

Subsea pipeline is the safest, most reliable, and most economical way to transport oil and gas from an offshore platform to an onshore terminal. However, the pipelines may rupture under the harsh working environment, causing oil and gas leakage. This calls for a proper device and method to detect the state of subsea pipelines in a timely and precise manner. The autonomous underwater vehicle carrying side-scan sonar offers a desirable way for target detection in the complex environment under the sea. As a result, this article combines the field-programmable gate array, featuring high throughput, low energy consumption and a high degree of parallelism, and the convolutional neural network into a sonar image recognition system. First, a training set was constructed by screening and splitting the sonar images collected by sensors, and labeled one by one. Next, the convolutional neural network model was trained by the set on the workstation platform. The trained model was integrated into the field-programmable gate array system and applied to recognize actual datasets. The recognition results were compared with those of the workstation platform. The comparison shows that the computational precision of the designed field-programmable gate array system based on convolutional neural network is equivalent to that of the workstation platform;however, the recognition time of the designed system can be saved by more than 77%, and its energy consumption can also be saved by more than 96.67%. Therefore, our system basically satisfies our demand for energy-efficient, real-time, and accurate recognition of sonar images.

关键词： Autonomous underwater vehicle field-programmable gate array convolutional neural network sonar image recognition

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Real-time field-programmable gate array-based closed-loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia

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CNS NEUROSCIENCE & THERAPEUTICS 2024年第3期30卷 e14638-e14638页

作者： Kumar, Gajendra Zhou, Zhanhong Wang, Zhihua Kwan, Kin Ming Tin, Chung Ma, Chi Him Eddie City Univ Hong Kong Dept Neurosci Hong Kong Peoples R China City Univ Hong Kong Dept Biomed Engn Hong Kong Peoples R China Chinese Univ Hong Kong Ctr Cell & Dev Biol Sch Life Sci Hong Kong Peoples R China Chinese Univ Hong Kong State Key Lab Agrobiotechnol Hong Kong Peoples R China City Univ Hong Kong Dept Neurosci Tat Chee Ave Hong Kong Peoples R China

Aims: The open-loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real-time field-programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC-specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits. Methods: We implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open-loop DCN-DBS or closed-loop DCN-DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real-time computation, was used for closed-loop DCN-DBS system. Results: Closed-loop DCN-DBS was triggered only when symptomatic muscle EMG was detected in a real-time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed-loop DCN-DBS was more effective than an open-loop paradigm as it reduced the frequency of DBS. Conclusion: Our real-time FPGA-based DCN-DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders.

关键词： cerebellar ataxia cerebellum deep brain stimulation electroencephalography electromyography field-programmable gate array

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Hardware implementation and performance analysis of MPTD-CSMA protocol based on field-programmable gate array in VANET

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IET COMMUNICATIONS 2020年第16期14卷 2769-2779页

作者： Ding, Hongwei Lu, Xu Li, Bo Wang, Liqing Bao, Liyong Yang, Zhijun Liu, Qianlin Yunnan Univ Sch Informat Kunming 650091 Yunnan Peoples R China

Contention-based carrier sense multiple access (CSMA) and contention-free time division multiple access (TDMA) protocol are two typical access protocols of media access control in vehicularad hocnetwork (VANET). They all show their unique advantages under specific conditions. TDMA has high transmission reliability, CSMA has a low transmission delay in the communication environment with low packet arrival rate. However, when the arrival rate of information packets increases rapidly, the throughput of CSMA will decrease rapidly and approach zero, which is not suitable for data transmission in the communication environment with a high arrival rate of information packets;while data transmission through a single TDMA protocol will cause high system overhead due to strict synchronous information. Aiming at the defects of the two protocols and the multi-channel communication environment, this study proposes the optimised protocol model multi-priority time division-CSMA (MPTD-CSMA). The optimised protocol model not only ensures the reliability of data communication but also reduces the transmission delay of the system. At the same time, the multi-priority mechanism is added to increase the channel utilisation of the protocol model.

关键词： protocols mobile radio vehicular ad hoc networks wireless channels data communication field programmable gate arrays carrier sense multiple access time division multiple access access protocols ad hoc networks VANET high transmission reliability low transmission delay low packet arrival rate information packets data transmission high arrival rate single TDMA protocol high system strict synchronous information multichannel communication environment optimised protocol model multipriority time division-CSMA data communication performance analysis MPTD-CSMA protocol field-programmable gate array contention-free time division typical access protocols media access control vehicular ad hoc network

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field-programmable gate array-Based Coating Impedance Detector for Rapid Evaluation of Early Degradation of Protective Coatings

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IEEE ACCESS 2019年 7卷 20472-20478页

作者： Lee, Yueh-Lien Kuo, Yu-Tong Chen, Hung-Hsun Hsieh, Yung-An Natl Taiwan Univ Dept Engn Sci & Ocean Engn Taipei 10617 Taiwan

In this paper, a novel, compact, And field-programmable gate array (FPGA)-based coating impedance detector (CID 2.0) was proposed to rapidly detect the early degradation of coatings. An FPGA-based hardware design with an embedded analog-to-digital converter and digital-to-analog converter was successfully applied to develop CID 2.0. A method for generating high-quality signals for FPGA by using the delta-sigma modulation was used. This method provided higher measurement ranges and accuracies for detecting coating impedance values. The performance of CID 2.0 was compared with that of a conventional potentiostat. For comparison, the impedance value of ideal resistors and commercial coatings was measured using the proposed and conventional methods. The results indicated an optimal correlation between the impedance values measured using CID 2.0 and that measured using conventional potentiostat in the range of 10(6) - 10(10) Omega-cm(2). Furthermore, when the continuous monitoring experiments were conducted, CID 2.0 exhibited high sensitivity to detect impedance changes associated with the coating delamination process. The preliminary results suggested that CID 2.0 can be used to observe the changes in the coating impedance values in the critical range to enable workers to determine whether coating maintenance should be scheduled.

关键词： Coating corrosion monitor electrochemical impedance spectroscopy impedance measurement field-programmable gate array

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Composition of magnetic tunnel junction-based magnetoresistive random access memory for field-programmable gate array

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CURRENT SCIENCE 2020年第1期119卷 119-123页

作者： Hamsa, S. Thangadurai, N. Ananth, A. G. Jain Deemed To Be Univ Elect & Commun Engn Dept Bengaluru 560112 India NMAMIT Elect & Commun Engn Dept Nitte 574110 Udupi India

In this study, the schematics for Magnetic Tunnel Junction-Magnetoresistive Random Access Memory (MTJ-MRAM) are designed and simulations are carried out in 45 and 90 nm Complementary Metal-Oxide Semiconductor (CMOS) Very Large Scale Integration (VLSI) technology using analog design environment. Other memory circuits like volatile Static Random Access Memory (SRAM) and non-volatile flash memory are designed and behavioural waveforms verified. The output behavioural characteristics of MTJ-MRAM are compared with that of SRAM and flash memory. The attributes like power and delay are calculated and compared with SRAM and flash memory circuits. The study was carried out in order to integrate the non-volatile memory with field-programmable gate array (FPGA) architecture and design a nonvolatile memory-based FPGA. MTJ-MRAM shows better performance than volatile SRAM and non-volatile flash memory in terms of power and delay parameters.

关键词： Behavioural waveforms field-programmable gate array magnetic tunnel junction memory circuits

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Time-of-flight ranging method by measuring pulse laser phase based on field-programmable gate array digital mixing

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MEASUREMENT SCIENCE AND TECHNOLOGY 2021年第2期32卷

作者： Tao, Min Gong, Xiaobin Hou, Yu Li, Baohua Song, Junfeng Chen, Jian Gao, Fengli Jilin Univ Coll Elect Sci & Engn State Key Lab Integrated Optoelect Changchun 130012 Peoples R China ShanheGensheng Technol Co Ltd Jilin Prov Jilin 132011 Jilin Peoples R China

We propose a time-of-flight ranging method by measuring the pulse laser phase based on field-programmable gate array (FPGA) digital mixing, in which accurate laser ranging with a total digital system is realized by combining one FPGA chip with a simple laser transmitting and receiving circuit. The system has the advantage of simple structure, reliable operation, low manufacturing cost and easy integration. Experimental results show that compared with the pulse laser ranging method using commercial time-to-digital converter chips, it can realize precise measurement of distance, and the measurement error can be significantly reduced. In addition, this method has better performance of ranging accuracy.

关键词： time-of-flight laser ranging field-programmable gate array digital mixing

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Real-time power monitoring using field-programmable gate array with IoT technology

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2019年第6期13卷 931-935页

作者： Lee, Kok Tong Mun, Hou Kit Southern Univ Coll Fac Engn & Informat Technol Skudai 81300 Johor Malaysia Taylors Univ Sch Engn 1 Jalan Taylors Subang Jaya 47500 Selangor Malaysia

Automation technologies are often impacted undesirably by downtime caused by machine failures. An approach to overcome machine failures is through failures prediction, achievable via the monitoring of power consumption. Unusual power consumption could serve as an alert for possible machines faults. Real-time power consumption monitoring is made possible with the deployment of Internet of Things (IoT), which brings together digital cloud computing and conventional automation technology to rapidly increase the efficiency of production. In this work, the authors have developed an IoT-based power monitoring system to detect unusual power consumption of machines and present the data to users remotely through Android application and cloud storage. The competent integration of Wi-Fi module ESP8266, CT sensor module and field-programmable gate array DE1-SoC board allows the system to accurately measure power consumption and instantaneously store the data in cloud storage. Performance of the developed system was characterised by current measurement of five different loads. The absolute errors, given by the difference between current measured by digital multimeter and the developed system, range from 0.01 to 0.26A. The close agreement between the two measurements endorses the accuracy and reliability of the real-time power monitoring system, on top of its easy-accessibility gifted by IoT.

关键词： system-on-chip wireless LAN power system measurement cloud computing field programmable gate arrays Internet of Things electric current measurement power consumption power engineering computing smart phones power system reliability field-programmable gate array cloud storage real-time power monitoring system IoT technology automation technologies machine failures failures prediction unusual power consumption possible machines faults real-time power consumption monitoring conventional automation technology IoT-based power monitoring system Internet of Things digital cloud computing Android application Wi-Fi module ESP8266 CT sensor module DE1-SoC board current measurement digital multimeter

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Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第5期13卷 405-413页

作者： Jaafar, Anuar Soin, Norhayati Hatta, Sharifah Wan Muhamad Irwan, Salim Sani Univ Teknikal Malaysia Melaka UTeM FKEKK Ctr Telecommun Res & Innovat CeTRI Durian Tunggal 76100 Melaka Malaysia Univ Malaya Fac Engn Dept Elect Engn Kuala Lumpur 50603 Malaysia Univ Malaya Ctr Printable Elect Kuala Lumpur 50603 Malaysia

Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100 degrees C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs.

关键词： field programmable gate arrays electromigration oscillators temperature sensors hot carriers clocks thermal variation field-programmable gate array stable ring oscillator thermal issues FGPAs digital temperature sensor thermal effect temperature environment negative bias temperature instability hot carrier injection electromigration accurate ring oscillator design measurement period degradation effect temperature-based FPGAs clock cycles

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Feasibility Analysis of Baseband Board Based on field programmable gate array 19

Feasibility Analysis of Baseband Board Based on Field Progra...

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5th International Conference on Computer and Technology Applications (ICCTA)

作者： Wang, Meile Zhang, Zhizhong Wang, Guangya Chongqing Univ Posts & Telecommun 2 Chongwen Rd Chongqing Peoples R China

ISBN: (纸本)9781450371810

The design of the baseband board for many types of instrumentation developed is limited to verify its feasibility by implementation. On this basis we propose a detailed feasibility analysis method before the design of the baseband board to prevent the waste of the manpower and time resources because of the shortage of chip resources, which provided a reference for the design of the baseband board. Firstly we determine the model of core processor based on LTE-A characteristics and baseband board requirements;then we focus on the storage capacity and bus capacity of the baseband board to ensure that the selected components have sufficient capacity and margin;fmally we prove the correctness of the feasibility analysis through the test on the baseband board, and it also provides the reference for other hardware chip selection.

关键词： field-programmable gate array feasibility LTE-A baseband board

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