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Dynamic centralized control and intelligent load management system of a remote residential building with V2H technology

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JOURNAL OF ENERGY STORAGE 2022年 52卷

作者： Elkholy, M. H. Metwally, Hamid Farahat, M. A. Nasser, M. Senjyu, Tomonobu Lotfy, Mohammed Elsayed Zagazig Univ Fac Engn Elect Power & Machines PO 44519 Zagazig Egypt Univ Ryukyus Dept Elect & Elect Engn Nishihara Okinawa 9030213 Japan Zagazig Univ Fac Engn Dept Elect & Commun Engn PO 44519 Zagazig Egypt

Energy is the main engine and the active element for all growth and development. It is the basic element for all sectors of the economy and a companion to human life. It is also not forgotten that most of the energy used in the whole world is traditional and unsustainable energy, as well as polluting the environment and causing harmful emissions. Sustainable is based primarily on environmental protection. Massive population growth is accompanied by a significant increase in energy consumption. Currently, most countries are turning to rely mainly on renewable energy sources. To achieve the maximum benefit from the energy, the tendency is to manage energy within the home to avoid the occurrence of energy losses. In this paper, an efficient home energy management system (HEMS) is proposed. This system is based on the use of a field-programmable gate array (FPGA) for home energy management. The proposed HEMS takes into account both generation and consumption as FPGA manages the feeding process through the sources. The prototype is implemented using Altera Cyclone IV EP4CE6 FPGA board using QUARTUS II software. The home is fed through PV, wind and fuel cells (FC) sources. If there is a shortage in energy production and the three sources are unable to cover the loads, the batteries enter into service to cover this shortage. If the sources and batteries are unable to cover the required loads, the EV contributes to covering the load, but with specific constraints set by the owner. The proposed HEMS works to control the feeding of the loads, as it schedules the feeding of the loads according to priority in the event of severe energy shortages and the inability of the sources, batteries and the EV to cover the loads. The experimental and simulation results proved the ability of the proposed system to respond to the demand by managing high energy consuming household appliances according to the pre-set priority.

关键词： field-programmable gate array Home energy management PV Wind Fuel cells

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FPGA-Based Processor for Continual Capacitive-Coupling Impedance Spectroscopy and Circuit Parameter Estimation

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SENSORS 2022年第12期22卷 4406-4406页

作者： Tsukahara, Akihiko Yamaguchi, Tomiharu Tanaka, Yuho Ueno, Akinori Tokyo Denki Div Elect Engn Sch Sci & Engn Saitama 3500394 Japan Tokyo Denki Univ Dept Elect & Elect Engn Tokyo 1208551 Japan

In principle, the recently proposed capacitive-coupling impedance spectroscopy (CIS) has the capability to acquire frequency spectra of complex electrical impedance sequentially on a millisecond timescale. Even when the measured object with time-varying unknown resistance R-x is capacitively coupled with the measurement electrodes with time-varying unknown capacitance C-x, CIS can be measured. As a proof of concept, this study aimed to develop a prototype that implemented the novel algorithm of CIS and circuit parameter estimation to verify whether the frequency spectra and circuit parameters could be obtained in milliseconds and whether time-varying impedance could be measured. This study proposes a dedicated processor that was implemented as field-programmable gate arrays to perform CIS, estimate R-x and C-x, and their digital-to-analog conversions at a certain time, and to repeat them continually. The proposed processor executed the entire sequence in the order of milliseconds. Combined with a front-end nonsinusoidal oscillator and interfacing circuits, the processor estimated the fixed R-x and fixed C-x with reasonable accuracy. Additionally, the combined system with the processor succeeded in detecting a quick optical response in the resistance of the cadmium sulfide (CdS) photocell connected in series with a capacitor, and in reading out their resistance and capacitance independently as voltages in real-time.

关键词： electrical impedance spectroscopy capacitive-coupling impedance spectroscopy field-programmable gate array

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HMLib: Efficient Data Transfer for HLS Using Host Memory 23

HMLib: Efficient Data Transfer for HLS Using Host Memory

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Proceedings of the 2023 ACM/SIGDA International Symposium on field programmable gate arrays

作者： Michael Lo Young-kyu Choi Weikang Qiao Mau-Chung Frank Chang Jason Cong University of California Los Angeles Los Angeles CA USA Inha University Incheon Republic of Korea

ISBN: (纸本)9781450394178

Streaming applications compose an important portion of the workloads that FPGAs may accelerate but suffer from inefficient data movement. The inefficiency stems from copying data indirectly into the FPGA DRAM rather than directly into its on-chip memory, substantially diminishing the end-to-end speedup, especially for small workloads (hundreds of kilobytes). AMD Xilinx's Host Memory IP (HMI) aims to address the data movement problem by exposing to the developer an High-Level Synthesis (HLS) interface that moves the data from the host directly to the FPGA's on-chip memory. However, using HMI purely for its interface without additional code changes incurred a 3.3x slowdown in comparison with the current programming model. The slowdown mainly originates from OpenCL call overhead and the kernel control logic unnecessarily switching states. To overcome these issues, we propose Host Memory Library (HMLib), an efficient HLS-based library that facilitates data transfer on behalf of the user. HMLib not only optimizes the runtime stack for efficient data transfer, but also provides HLS compatible and user-friendly interfaces. We demonstrate HMLib's effectiveness for streaming applications (Deflate compression and CRC32) with improvements of up to up to 36.2X over OpenCL-DDR and up to 79.5X over raw HMI for small-scale data while maintaining little-to-no performance loss for large scale inputs. We plan to open source our work in the future.

关键词： high-level synthesis field-programmable gate array on-chip memory host memory opencl streaming workload

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Design of a Low-Power Embedded System Based on a SoC-FPGA and the Honeybee Search Algorithm for Real-Time Video Tracking

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SENSORS 2022年第3期22卷 1280页

作者： Soubervielle-Montalvo, Carlos Perez-Cham, Oscar E. Puente, Cesar Gonzalez-Galvan, Emilio J. Olague, Gustavo Aguirre-Salado, Carlos A. Cuevas-Tello, Juan C. Ontanon-Garcia, Luis J. Univ Autonoma San Luis Potosi UASLP Fac Ingn Dr Manuel Nava 8Zona Univ Poniente San Luis Potosi 78290 San Luis Potosi Mexico Ctr Invest Cient & Educ Super Ensenada CICESE Carretera Ensenada Tijuana 3918Zona Playitas Ensenada 22860 Baja California Mexico Univ Autonoma San Luis Potosi UASLP Coordinac Acad Reg Altiplano Oeste Carretera Salinas Santo Domingo 200 San Luis Potosi 78600 San Luis Potosi Mexico

Video tracking involves detecting previously designated objects of interest within a sequence of image frames. It can be applied in robotics, unmanned vehicles, and automation, among other fields of interest. Video tracking is still regarded as an open problem due to a number of obstacles that still need to be overcome, including the need for high precision and real-time results, as well as portability and low-power demands. This work presents the design, implementation and assessment of a low-power embedded system based on an SoC-FPGA platform and the honeybee search algorithm (HSA) for real-time video tracking. HSA is a meta-heuristic that combines evolutionary computing and swarm intelligence techniques. Our findings demonstrated that the combination of SoC-FPGA and HSA reduced the consumption of computational resources, allowing real-time multiprocessing without a reduction in precision, and with the advantage of lower power consumption, which enabled portability. A starker difference was observed when measuring the power consumption. The proposed SoC-FPGA system consumed about 5 Watts, whereas the CPU-GPU system required more than 200 Watts. A general recommendation obtained from this research is to use SoC-FPGA over CPU-GPU to work with meta-heuristics in computer vision applications when an embedded solution is required.

关键词： heterogeneous computing meta-heuristic video tracking system-on-chip field-programmable gate array evolutionary computing swarm intelligence embedded system design graphics processing unit computer vision

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Special-purpose computer for digital holographic high-speed three-dimensional imaging

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OPTICAL ENGINEERING 2020年第5期59卷

作者： Yamamoto, Yota Namba, Shintaro Kakue, Takashi Shimobaba, Tomoyoshi Ito, Tomoyoshi Masuda, Nobuyuki Chiba Univ Grad Sch Engn Chiba Japan Tokyo Univ Sci Fac Ind Sci & Technol Tokyo Japan

Digital holography is attracting attention because it can record instantaneous three-dimensional (3D) information and record dynamic phenomena. However, when recording highspeed phenomena, the frame rate ranges from tens of thousands to hundreds of millions, and the calculation time of the reconstructed images is a problem. We have developed a special-purpose computer for high-speed 3D imaging using digital holography. The developed special-purpose computer has four calculation modules and has achieved a calculation time 68 times faster than that of a personal computer with 48 cores. With the developed computer, a total of 32 reconstructed images can be calculated in 0.69 ms from four holograms of 128 x 128 pixels with eight varying depths. (C) The Authors. Published by SPIE under a Creative Commons Attribution 4.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

关键词： optics digital holography high-speed three-dimensional imaging field-programmable gate array

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Digitally controlled GaN-based MHz active clamp flyback converter with dynamic dead time optimisation for AC-DC adapter

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IET POWER ELECTRONICS 2020年第16期13卷 3777-3786页

作者： Gu, Donglie Xi, Jianxiong He, Lenian Zhejiang Univ Coll Elect Engn Hangzhou Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou Peoples R China

The active clamp flyback (ACF) converter utilising gallium nitride (GaN) devices with high-switching frequency and high efficiency is impressive in system miniaturisation for AC-DC adapters. Owing to poor reverse conduction of GaN devices, the improper dead time between two switches can cause large power consumption in high frequency. This study proposes a dynamic dead time optimisation technique for GaNs ideal zero-voltage switching (ZVS) to address the issue. It adjusts the clamp switch on time to avoid large reverse conduction voltage stress on the main switch in different loads conditions. In addition, a new control scheme for clamp switch is introduced for enhancing efficiency in light to medium load. These techniques are experimentally verified on a 45 W (20 V/2.25 A) prototype of an ACF converter with a field-programmable gate array. The controller enables the system to operate at 1 MHz and dynamically modulates the dead-time under universal input and full load. With the light load ZVS control scheme, the system can achieve a maximum efficiency of 94.12 and 80.23% in the worst case. The prototyped converter can achieve power density (exclude case and controller) of 18 W/in(3).

关键词： field programmable gate arrays switching convertors III-V semiconductors gallium compounds zero voltage switching wide band gap semiconductors digital control AC-DC power convertors circuit optimisation switches zero-voltage switching clamp switch reverse conduction voltage stress main switch load conditions ACF converter light load ZVS control scheme AC-DC adapter high-switching frequency system miniaturisation dynamic dead time optimisation technique digitally controlled gallium nitride-based MHz active clamp flyback converter gallium nitride devices power consumption field-programmable gate array power density full load universal input load power 45 0 W voltage 20 0 V current 2 25 A frequency 1 0 MHz power 18 0 W GaN

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XNORCONV: CNNs accelerator implemented on FPGA using a hybrid CNNs structure and an inter-layer pipeline method

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IET IMAGE PROCESSING 2020年第1期14卷 105-113页

作者： Zhang, Lin Bu, Xiaokang Li, Bing Southeast Univ Sch Integrated Circuits 2 Sipai Lou Nanjing Peoples R China

Nowadays, convolutional neural networks (CNNs) have become a research hotspot because of their high performance in computer vision and pattern recognition. However, as the high energy consumption of traditional graphic processing units-based CNNs, it is difficult to deploy them into portable devices. To deal with this problem, a hybrid CNN structure (XNORCONV) was proposed and implemented on field-programmable gate array (FPGA) in this study. Two improvements have been applied in XNORCONV. Firstly, the multiplications in the convolutional layer (CONV) were replaced by XNOR operations to save the multiplier and reduce computational complexity. Secondly, an inter-layer pipeline was designed to further accelerate the calculation. XNORCONV was implemented on Xilinx Zynq-7000 xc7z020clg400-1 under the clock frequency of 150 MHz and tested with MNIST dataset. The results of the experiment show that XNORCONV can classify each picture from MNIST in $ 18 .97\, {\rm \mu s}$18.97 mu s, and achieve 98.4% recognition accuracy. Compared with traditional Lenet-5 on different platforms, XNORCONV reduced multiplication by 85.6% with only 0.4% accuracy loss.

关键词： field programmable gate arrays logic gates convolutional neural nets neural chips multiplying circuits computational complexity pipeline processing logic design XNORCONV CNNs accelerator FPGA hybrid CNNs structure convolutional neural networks computer vision pattern recognition energy consumption graphic processing units-based CNNs field-programmable gate array convolutional layer XNOR operations multiplier computational complexity inter-layer pipeline design Xilinx Zynq-7000 xc7z020clg400-1 clock frequency MNIST dataset

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An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2020年第3期28卷 1656-1672页

作者： Ben Atitallah, Ahmed Kammoun, Manel Ben Atitallah, Rabie Jouf Univ Dept Elect Engn Aljouf Saudi Arabia Univ Sfax LETI ENIS Sfax Tunisia Galatasaray Univ Dept Comp Sci Istanbul Turkey

This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 x 4, 8 x 8, 16 x 16, and 32 x 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standard-cells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) environment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

关键词： High-efficiency video coding decoder IDCT inverse quantization software/hardware environment field-programmable gate array

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Electronic Interpolation Interface Based on Linear Subdivision Method for Sinusoidal Optical Encoders

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IEEE SENSORS JOURNAL 2020年第7期20卷 3646-3654页

作者： Zhao, Guobo Ye, Guoyong Liu, Hui Lei, Biao Li, Xuan Han, Weiliang Liu, Hongzhong Xi An Jiao Tong Univ State Key Lab Mfg Syst Engn Xian 710049 Peoples R China

Sinusoidal optical encoders are widely utilized in precision positioning systems. With the development of precision positioning systems, higher resolution is required. Electronic interpolation is a promising technique to further improve the resolution of sinusoidal optical encoders. In this paper, we propose an electronic interpolation interface based on linear subdivision method with better practical accuracy. Firstly, a pseudo-linearized signal based on the difference between the absolute values of sine and cosine signals is generated. Then, a compensation signal with a ratiometric form is constructed, which has a better robustness to the non-ideal input signals. Finally, a nearly perfect linear output signal is obtained by combining these two signals. Thus, the displacement can be linearly determined without LUTs. It is shown that the theoretical nonlinear error of the proposed method is below 0.08 degrees over a signal period of 360 degrees, which corresponds to a theoretical interpolation error of 0.018 mu m for sinusoidal optical encoders with a pitch of 80 mu m. Moreover, theoretical analysis and simulation results indicate that the proposed method offers a better practical accuracy. In the experiment, the proposed electronic interpolation interface is developed in a field-programmable gate array (FPGA), and experiments are carried out to evaluate its performance. Both the theoretical and experiment results verify its effectiveness.

关键词： Sinusoidal optical encoder linearization technique electronic interpolation precision phase solution field-programmable gate array

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Implementation of modulation classifier over software defined radio

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IET COMMUNICATIONS 2020年第9期14卷 1467-1475页

作者： Jajoo, Gaurav Kumar, Yogesh Kumar, Ashok Yadav, Sandeep Kumar Dept Elect Engn NH 65 Jodhpur Rajasthan India DRDO Sci Anal Grp Sag Delhi India

Blind signal modulation recognition is an essential block for designing a cognitive radio. Different algorithms are developed in the literature, but few are given with detailed implementation. This study proposes a software-defined radio based implementation of blind signal modulation recogniser (BSMR) on field-programmable gate array (FPGA), which works without any prior knowledge of the received signal. The algorithm estimates carrier frequency offset, symbol rate, symbol timing offset, and corrects the signal for these offsets to extract constellation points. It uses clustering structure formed by constellation signature in I/Q plane to detect the modulation for different orders of ASK, PSK, and QAM. The proposed algorithm is deployed on FPGA, using LabVIEW, for a reliable and reconfigurable platform. The algorithm is optimised to use minimum hardware resources and facilitate future up-gradation. The system developed by implementing the algorithm on NI-FlexRIO-7975 FPGA module with NI-5791 adapter detects modulation type in real time without any training. Signals for testing are generated using NI-PXIe-5673 (RF transmitter), and BSMR identifies the modulation type in 81.451ms under additive white Gaussian noise channel.

关键词： virtual instrumentation phase shift keying cognitive radio field programmable gate arrays quadrature amplitude modulation AWGN channels software radio amplitude shift keying pattern classification pattern clustering BSMR modulation classifier blind signal modulation recognition cognitive radio software-defined radio blind signal modulation recogniser field-programmable gate array received signal carrier frequency offset symbol rate symbol timing offset constellation points constellation signature NI-FlexRIO-7975 FPGA module NI-5791 adapter clustering structure ASK PSK QAM LabVIEW reconfigurable platform RF transmitter additive white Gaussian noise channel

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