检索结果-内蒙古大学图书馆

High-Speed Real-Time Simulation for Power Electronic Systems

SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL 2008年第8-9期84卷 441-456页

作者： Word, Dale Bednar, Richard Zenor, John J. Hingorani, Nari G. Calif State Univ Chico Dept Elect & Comp Engn Chico CA 95929 USA Calif State Univ Chico McLeod Inst Simulat Sci Chico CA 95929 USA Independent Consultant Los Altos Hills CA 94022 USA

Real-time simulators have been used as an aid to power system design for many years. Over time, scaled-down physical models and analog computer-based simulators have given way to real-time simulators based on digital technology. Another trend has been the need for shorter and shorter frame times for these digital real-time simulators. Modern power electronic systems use high-frequency Pulse-Width Modulated (PWM) controllers. Indications are that frame times of 2 mu S are needed for PWM switching frequencies of 10 KHz. As frequencies increase further it is possible that frame times of less than 1 mu S may be required. In order to achieve these very short frame times, the implementation of this type of simulator requires careful selection of the methods and technologies used. The first involves thorough analysis of the integration method chosen, to ensure that it provides the performance, stability and accuracy required. Additionally, the choice of computing platform is crucial to provide the computational support to meet these very aggressive timing requirements.

关键词： simulation power electronics real-time Digital Signal Processors field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

DRAF: A LOW-POWER DRAM-BASED RECONFIGURABLE ACCELERATION FABRIC

引用

IEEE MICRO 2017年第3期37卷 70-78页

作者： Gao, Mingyu Delimitrou, Christina Niu, Dimin Malladi, Krishna T. Zheng, Hongzhong Brennan, Bob Kozyrakis, Christos Stanford Univ Dept Elect Engn Stanford CA 94305 USA Cornell Univ Dept Elect & Comp Engn Ithaca NY 14853 USA Cornell Univ Dept Comp Sci Ithaca NY 14853 USA Samsung Semicond US R&D Ctr Memory Solut Lab San Jose CA USA Stanford Univ Dept Comp Sci Stanford CA 94305 USA

The DRAM-Based Reconfigurable Acceleration Fabric (DRAF) uses commodity DRAM technology to implement a bit-level, reconfigurable fabric that improves area density by 10 times and power consumption by more than 3 times over conventional field-programmable gate arrays. Latency overlapping and multicontext support allow DRAF to meet the performance and density requirements of demanding applications in datacenter and mobile environments.

关键词： DRAM field-programmable gate array FPGA low power reconfigurable logic

来源：评论

学校读者我要写书评

暂无评论

LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference

引用

IEEE TRANSACTIONS ON COMPUTERS 2020年第12期69卷 1795-1808页

作者： Wang, Erwei Davis, James J. Cheung, Peter Y. K. Constantinides, George A. Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England

Research has shown that deep neural networks contain significant redundancy, and thus that high classification accuracy can be achieved even when weights and activations are quantized down to binary values. Network binarization on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We describe the realization of both unrolled and tiled LUTNet architectures, with the latter facilitating smaller, less power-hungry deployment over the former while sacrificing area and energy efficiency along with throughput. For both varieties, we demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarized neural network implementation, we achieve up to twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable.

关键词： Deep neural network hardware architecture field-programmable gate array lookup table

来源：评论

学校读者我要写书评

暂无评论

Wavelet-based Methodology for Broken Bar Detection in Induction Motors with Variable-speed Drive

引用

ELECTRIC POWER COMPONENTS AND SYSTEMS 2011年第3期39卷 271-287页

作者： Millan-Almaraz, J. R. Romero-Troncoso, R. J. Osornio-Rios, R. A. Garcia-Perez, A. Univ Autonoma Queretaro Fac Ingn Lab Biosistemas Div Estudios Posgrado Queretaro 76010 Qro Mexico Univ Guanajuato CA Telemat DICIS CA Procesamiento Digital Senales Guanajuato Mexico Univ Autonoma Queretaro Fac Ingn CA Mecatron San Juan Del Rio Queretaro Mexico

Preventive maintenance and monitoring of induction motors is mandatory for industries. Broken rotor bars are among the most common failures in induction motors. Several techniques to detect broken bars have been reported;however, they focus on motors connected directly to the power supply and do not consider the case for motors connected through variable-speed drives, where detectability becomes ineffective. The novelty of this work consists of a new methodology based on multiple discrete wavelet transforms implemented in a field-programmable gate array, which is able to detect broken rotor bars in direct-line and variable-speed drives fed at various motor operating speeds. Several tests were performed, and results show the system effectiveness.

关键词： broken rotor bar field-programmable gate array induction motor variable-speed drive wavelet transform

来源：评论

学校读者我要写书评

暂无评论

FPGA partitioning with complex resource constraints

引用

VLSI DESIGN 2000年第3期11卷 219-235页

作者： Liu, HQ Zhu, K Wong, DF Univ Texas Dept Comp Sci Austin TX 78712 USA Actel Corp Sunnyvale CA 94086 USA

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g., Actel's ES6500 FPGA family).

关键词： field-programmable gate array circuit partitioning heterogeneous logic block hierarchical FPGA architecture

来源：评论

学校读者我要写书评

暂无评论

A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems

引用

APPLIED SOFT COMPUTING 2007年第3期7卷 979-994页

作者： Salcic, Zoran Coghill, George Maunder, Bruce Univ Auckland Dept Elect & Comp Engn Auckland New Zealand

In this paper we present a methodology for optimizing complex datapath oriented digital circuits. An optimizer was developed based on the earlier development of an automatic circuit synthesizer that synthesizes hardware description language specifications based on available functional modules. A genetic algorithm is tailored to the problem of digital circuit optimization through the development of specific structures and procedures. In particular, a concise encoding of the circuit is developed that the genetic algorithm can manipulate. Specific crossover and mutation mechanisms are also developed to complement the functionality of the synthesizer. The searches are effected by altering module data type, hardware resource sharing, and module implementation version. A fitness function is derived that makes use of a number of optimization parameters to objectively evaluate each particular circuit. The features of each circuit are calculated and estimated during the analysis phase. (c) 2006 Elsevier B. V. All rights reserved.

关键词： optimization data-flow genetic algorithm high-level synthesis field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Electrical and optical clock and data recovery in optical access networks: a comparative study

引用

INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS 2016年第17期29卷 2555-2564页

作者： Abd El-Khaleq, Esraa El-Sayed, Yasmine Ismail, Tawfik Mostafa, Hassan Cairo Univ Dept Elect & Commun Fac Engn Giza Egypt Cairo Univ Natl Inst Laser Enhanced Sci Dept Engn Applicat Laser Giza Egypt

Clock and data recovery (CDR) is an essential part in high-speed telecommunication systems. The CDR is used to extract the clock and re-time the received data, which allows a synchronous operation to recover the transmitted signal. In optical access networks, electrical CDR or optical CDR implementations can be used. However, there are no clear guidelines or recommendations on which CDR implementation should be adopted for better performance. These missing clear recommendations are because the electrical CDR requires electronics design expertise whereas the optical CDR requires optical design expertise. Consequently, in this paper, an all-digital CDR, designed and implemented on the field-programmable gate array platform, and an optical CDR, developed by using fiber Bragg grating technology on the OptiSystem platform, are presented. Furthermore, the integration of these 2 CDR implementations with the optical access network is implemented, and their performance is evaluated for various transmission rates and communication distances. Finally, a comparative study in terms of the bit error rate between the all-digital CDR and the optical CDR is presented.

关键词： clock and data recovery fiber Bragg grating field-programmable gate array optical access network

来源：评论

学校读者我要写书评

暂无评论

LED dimming with efficiency considered

引用

ELECTRONICS LETTERS 2011年第7期47卷 457-458页

作者： Hwu, K. I. Tu, W. C. Natl Taipei Univ Technol Dept Elect Engn Taipei 10608 Taiwan

A LED dimming circuit, together with the KY converter, is presented, which is controlled based on a field-programmable gate array. Via the proposed feedback control strategy, the voltage across the linear current regulator is reduced so as to upgrade the efficiency of the overall system, with the proposed maximum error selection based on a suitable voltage turning on the diode. Aside from this, each LED string takes direct dimming, and is powered by the KY converter, which has an output inductor and hence upgrades the life of the output capacitor. Experimental results show that the efficiency based on the proposed control method is higher than that based on the traditional control one, particularly at light load.

关键词： LED dimming field programmable gate arrays field-programmable gate array light emitting diodes linear current regulator voltage regulators voltage turning

来源：评论

学校读者我要写书评

暂无评论

20-Bit RISC and DSP System Design in an FPGA

引用

COMPUTING IN SCIENCE & ENGINEERING 2014年第2期16卷 16-20页

作者： Tomar, Amit Kumar Singh Jain, Rita Lakshmi Narain College of Technology India

Today, most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer core with several operations performed by a digital signal processor system. Here, the design of a RISC and DSP system is presented that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA). This RISC is a 20-bit processor.

关键词： ALU CPU CU FPGA GPR IR MACs PC RISC RS VLIW arithmetic logic unit control unit field-programmable gate array general-purpose register instruction register multiply and accumulates program counter reduced instruction set computer register set scientific computing very large instruction word

来源：评论

学校读者我要写书评

暂无评论

FPGA implementation of AES encryptor based on rolled and masked approach

引用

INTERNATIONAL JOURNAL OF INFORMATION AND COMPUTER SECURITY 2023年第1-2期21卷 1-18页

作者： Mathur, Monika Goel, Nidhi IGDTUW Dept ECE Kashmere Gate Delhi India

The present work proposes a modified 8-bit AES architecture that performs AES core operations in a single round wherein data is iterated ten times instead of having ten different rounds leading to substantial decrease in area and power consumption. To enhance the security of AES encryption, boolean masking has been employed for all AES operations, rounds and intermediate data. Modified architecture for AddRoundKey and ByteSubstitution operation has been proposed that employs high order masking. Also, an enhanced key expansion algorithm is proposed that makes AES less vulnerable to saturation attacks and differential power analysis (DPA) attacks. Implementation of the proposed architecture has been done using Vivado Design Suite on Virtex-7 FPGA. Result analysis depicts that, during the performance explore strategy, 179.73 MHz maximum frequency with a throughput of 143.78 Mbps has been achieved whereas, the proposed architecture utilises 757 slices, 962 LUTs and 0.313 watt power using area explore strategy.

关键词： advanced encryption standard AES field-programmable gate array FPGA Boolean masking enhanced key expansion algorithm DPA attack rolled architecture

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：