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Development of a digital interpolation module for high-resolution sinusoidal encoders

SENSORS AND ACTUATORS A-PHYSICAL 2019年 285卷 501-510页

作者： Ye, Guoyong Wu, Zeze Xu, Zhengchen Wang, Yang Shi, Yongsheng Liu, Hongzhong Xi An Jiao Tong Univ State Key Lab Mfg Syst Engn Xian 710049 Shaanxi Peoples R China

This paper presents a digital interpolation module for high-resolution sinusoidal encoders. The proposed strategy performs phase-shifting manipulation on the sinusoidal encoder signals, and takes advantage of the linear sections of the absolute values of the phase-shifted sinusoidal signals. Thus, an approximately linear signal is obtained, from which the displacement can be linearly determined. Simulation result shows that the theoretical error of the proposed interpolate strategy is within 0.072 degrees over the 360 degrees signal period. Furthermore, a digital interpolation module is developed by implementing the interpolate strategy in a field-programmable gate array (FPGA), and performance evaluation experiments are carried out by applying it to a linear optical encoder with a pitch of 20 mu m. The effectiveness of the digital interpolation module has been validated by both simulation results and experimental results. (C) 2018 Published by Elsevier B.V.

关键词： Sinusoidal encoders Digital interpolation field-programmable gate array Signal linearization Phase-shifting manipulation High-resolution

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Modelling and control of dual input boost converter with voltage multiplier cell

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IET CIRCUITS DEVICES & SYSTEMS 2019年第8期13卷 1267-1276页

作者： Appikonda, Mohan Kaliaperumal, Dhanalakshmi Natl Inst Technol Dept Elect & Elect Engn Tiruchirappalli 620015 Tamil Nadu India Natl Inst Technol Dept Instrumentat & Control Engn Tiruchirappalli 620015 Tamil Nadu India

A dual input DC-DC converter with dual boost and integrated voltage multiplier cell operating at duty cycles larger than 0.5 is a necessity to achieve a high voltage gain for energy systems possessing two independent renewable energy resources. Output voltage regulation during load changes and input disturbances is the requisite of an energy system, which is achieved by the implementation of a suitable control action, which further requires the dynamic model of the converter. The modelling of this higher order converter with overlapping switching signals is complicated. The small-signal transfer function model based on state-space averaging followed by small-signal linearisation is verified using MATLAB and powersim (PSIM). The output voltage to duty cycle transfer functions significantly contributes to representing the converter dynamics from which its right-half s-plane zero is analysed. Since it is a non-minimum phase system, a dual loop control strategy is adopted. Voltage regulation and active current sharing are ensured from the simulation and experimental responses of the uncompensated and compensated systems. Further, from the derived integer-order converter model a fractional controller is designed and its dynamic response is compared with the traditional controller. A 200 W prototype of the converter is developed, and the control is implemented using field-programmable gate array.

关键词： field programmable gate arrays transfer functions DC-DC power convertors voltage control voltage regulators voltage multipliers dynamic response renewable energy sources linearisation techniques load changes input disturbances energy system dynamic model higher order converter overlapping switching signals small-signal transfer function model state-space averaging small-signal linearisation duty cycle transfer functions converter dynamics nonminimum phase system dual loop control strategy uncompensated systems fractional controller dynamic response dual input boost converter dual input DC-DC converter dual boost integrated voltage multiplier cell duty cycles voltage gain independent renewable energy resources output voltage regulation integer-order converter model field-programmable gate array power 200 0 W

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Acceleration of FPGA Based Convolutional Neural Network for Human Activity Classification Using Millimeter-Wave Radar

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IEEE ACCESS 2019年 7卷 88917-88926页

作者： Lei, Peng Liang, Jiawei Guan, Zhenyu Wang, Jun Zheng, Tong Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China Beihang Univ Sch Cyber Sci & Technol Beijing 100191 Peoples R China

Deep learning techniques have attracted much attention in the radar automatic target recognition. In this paper, we investigate an acceleration method of the convolutional neural network (CNN) on the field-programmable gate array (FPGA) for the embedded application of the millimeter-wave (mmW) radar-based human activity classification. Considering the micro-Doppler effect caused by a person's body movements, the spectrogram of mmW radar echoes is adopted as the CNN input. After that, according to the CNN architecture and the properties of the FPGA implementation, several parallel processing strategies are designed as well as data quantization and optimization of classification decision to accelerate the CNN execution. Finally, comparative experiments and discussions are carried out based on a measured dataset of nine individuals with four different actions by using a 77-GHz mmW radar. The results show that the proposed method not only maintains the high classification accuracy but also improves its execution speed, memory requirement, and power consumption. Specifically, compared with the implementation of the same network model on a graphics processing unit, it could achieve the speedup of about 30.42% at the cost of the classification accuracy loss of only 0.27%.

关键词： Human activity classification millimeter-wave radar convolutional neural network field-programmable gate array acceleration

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Integrated synchronous data acquisition subsystem for high-speed GPR system

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IET CIRCUITS DEVICES & SYSTEMS 2019年第7期13卷 1049-1055页

作者： Xu, Xianlei Xia, Tian Ma, Zheng Huston, Dryver China Univ Min & Technol Beijing State Key Lab Coal Resources & Safe Min Beijing 100083 Peoples R China State Key Lab Water Resource Protect & Utilizat C Beijing 100083 Peoples R China Univ Vermont Dept Mech Engn Coll Engn & Math Burlington VT 05405 USA

In this study, an integrated synchronous data acquisition subsystem for high-speed dual-channel ultra-wideband ground penetrating radar (GPR) system is designed and tested. Factors that could cause data missing and asynchronisation are analyzed. According to timing sequence, a field-programmable gate array-based onboard digital control module is integrated to synchronise the data acquisition and data storage subsystems. By applying simultaneous multi-buffer acquisition and readout mode and multi-threading configuration, as well as the critical section control and queue storage structure, the GPR data throughput is considerably improved. For the practicality of this system, a smart End-of-Job control design is performed between different threads to control data acquisition. By using different performance indexes, receiver operation characteristic curve, maximum scan rate, and the rebar detection experiment demonstrate the superiority of author's method.

关键词： data acquisition ground penetrating radar ultra wideband radar field programmable gate arrays integrated synchronous data acquisition subsystem high-speed GPR system data storage subsystems readout mode GPR data throughput field-programmable gate array smart end-of-job control design ground penetrating radar system high-speed dual-channel ultra-wideband radar system timing sequence onboard digital control module multithreading configuration critical section control queue storage structure receiver operation characteristic curve maximum scan rate rebar detection

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Ultra-Low Complex Blind I/Q-Imbalance Compensation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2019年第9期66卷 3517-3530页

作者： Paireder, Thomas Motz, Christian Kanumalli, Ram S. Sadjina, Silvester Huemer, Mario Intel DMCE A-4040 Linz Austria Johannes Kepler Univ Linz Christian Doppler Lab Digitally Assisted RF Trans A-4040 Linz Austria

Direct-conversion transceivers are the predominating architecture in current mobile communication systems. Despite many advantages, this topology suffers from unavoidable mismatches in the analog part, which causes imbalance between the in-phase and quadrature (I/Q) component. In this paper, we present a novel fully digital, blind I/Q imbalance compensation algorithm that features extremely low computational complexity and high compensation performance for a wide range of input signal types. Different to many state-of-the-art compensation schemes, the approach is not based on a gradient descent optimization and does not require any global feedback. This simplifies the implementation at high data rates and reduces the configuration effort to a minimum. For comparison, we examine an existing method of moment-based estimator with similar properties, for which we also provide the detailed insights beyond available literature. For both algorithms, we provide a rigorous mathematical analysis, which is supported by simulations with a focus on various long-term evolution (LTE) signal types. In addition, hardware architectures, including field-programmable gate array (FPGA) verification, are presented for both algorithms.

关键词： Amplitude and phase imbalance image attenuation long-term evolution direct conversion transceiver field-programmable gate array

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Efficient Design and Implementation of Energy Detection-Based Spectrum Sensing

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2019年第11期38卷 5187-5211页

作者： Yadav, Pratik V. Alimohammad, Amirhossein Harris, Fred Universal Elect Inc San Diego CA 92121 USA San Diego State Univ Dept Elect & Comp Engn San Diego CA 92182 USA Univ Calif San Diego Dept Elect & Comp Engn San Diego CA 92103 USA

Cognitive radio allows opportunistic spectrum access by finding and using temporally and spatially unused radio channels to enhance the utilization of scarce radio spectrum. Various spectrum sensing techniques have been proposed to detect the availability of unoccupied radio channels. In this article, we first briefly discuss the merits of various spectrum sensing techniques. We then present an efficient hardware architecture for energy detection-based spectrum sensing. We discuss various design parameters and features, such as transform length, window selection, window overlap, ensemble averaging, and dynamic thresholding for efficient realization of the designed spectrum sensing module. Then, an efficient hardware architecture for an optimal energy detection-based spectral estimator is presented. To reduce the computational complexity, we utilize a polyphase filter structure. For the high-performance implementation of the proposed spectrum sensing architecture, we use cutset retiming, and for the compact realization, we use the time-multiplexing technique to reuse hardware resources. We model our spectrum sensing module in both floating-point and fixed-point representations using our custom-developed library of numerical operations. The synthesizable parameteric model of the energy detection-based spectrum sensing module is developed in Verilog hardware description language. The architecture of the designed spectrum sensing module is implemented on a Xilinx Virtex-7 field-programmable gate array and operates at 327 MHz. The cycle-accurate bit-true hardware simulation results are verified against its fixed-point software simulation results. An ASIC architecture of the designed spectrum sensing module is estimated to occupy 5.65mm(2) and dissipate 9.10 mW from a 1.05-V supply while operating at 200 MHz in a standard 32-nm CMOS technology for a 200 MHz bandwidth.

关键词： Spectrum sensing Cognitive radio field-programmable gate array Application-specific integrated circuit

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FPGA-Based Implementation of Finite Set-MPC for a VSI System Using XSG-Based Modeling

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ENERGIES 2020年第1期13卷 260页

作者： Singh, Vijay Kumar Tripathi, Ravi Nath Hanamoto, Tsuyoshi Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Fukuoka 8080196 Japan Kyushu Inst Technol Next Generat Power Elect Res Ctr Fukuoka 8080196 Japan

Finite set-model predictive control (FS-MPC) is used for power converters and drives having unique advantages as compared to the conventional control strategies. However, the computational burden of the FS-MPC is a primary concern for real-time implementation. field programmable gate array (FPGA) is an alternative and exciting solution for real-time implementation because of the parallel processing capability, as well as, discrete nature of the hardware platform. Nevertheless, FPGA is capable of handling the computational requirements for the FS-MPC implementation, however, the system development involves multiple steps that lead to the time-consuming debugging process. Moreover, specific hardware coding skill makes it more complex corresponding to an increase in system complexity that leads to a tedious task for system development. This paper presents an FPGA-based experimental implementation of FS-MPC using the system modeling approach. Furthermore, a comparative analysis of FS-MPC in stationary alpha beta and rotating dq frame is considered for simulation as well as experimental result. The FS-MPC for a three-phase voltage source inverter (VSI) system is developed in a realistic digital simulator integrated with MATLAB-Simulink. The simulated controller model is further used for experimental system implementation and validation using Xilinx FPGA: Zedboard Zynq Evaluation and Development Kit. The digital simulator termed as Xilinx system generator (XSG) provided by Xilinx is used for modeling-based FPGA design.

关键词： field-programmable gate array finite set-model predictive control model-based design voltage source inverter Xilinx system generator

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Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices

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MICROELECTRONICS JOURNAL 2019年第Jan.期83卷 39-49页

作者： Suzuki, Daisuke Oka, Takahiro Hanyu, Takahiro Tohoku Univ Frontier Res Inst Interdisciplinary Sci Sendai Miyagi 9808578 Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi 9808577 Japan

A circuit optimization technique of nonvolatile logic-in-memory (NVLIM)-based lookup table (LUT) circuits in conjunction with magnetic-tunnel junction (MTJ) devices is proposed. Three important points should be considered for the circuit optimization technique of the NVLIM-based LUT circuit. One is optimizing DC and transient characteristics of the read current path, another is minimizing the effect of capacitance of both read-access transistors and write-access transistors, the other is how to design the selector circuit. As a typical example, the NVLIM-based LUT circuits is designed using 55 nm CMOS technology with two types of MTJ devices;the output delay, power and area of the circuit are evaluated. As a result, the output delay in the NVLIM-based 6-input LUT circuit is reduced by 47% compared to that of conventional SRAM-based implementation with 27% lower active power consumption as well as 67% of area reduction.

关键词： Magnetic tunnel junction device field-programmable gate array Lookup-table circuit Circuit optimization

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FPGA-based implementation of different families of fractional-order chaotic oscillators applying Grunwald-Letnikov method

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COMMUNICATIONS IN NONLINEAR SCIENCE AND NUMERICAL SIMULATION 2019年第Jun.期72卷 516-527页

作者： Dalia Pano-Azucena, Ana Ovilla-Martinez, Brisbane Tlelo-Cuautle, Esteban Manuel Munoz-Pacheco, Jesus Gerardo de la Fraga, Luis INAOE Dept Elect Puebla 72840 Mexico Univ Autonoma Metropolitana Unidad Iztapalapa Mexico City 09340 DF Mexico BUAP Fac Elect Sci Puebla 72570 Mexico CINVESTAV Comp Sci Dept Mexico City 07360 DF Mexico

Fractional-order chaotic oscillators are a hot topic of research and nowadays many new mathematical models have been introduced, which can be suitable for the development of novel applications in all related fields of science and engineering. However, the challenge is their implementation that can be performed using electronic devices. In this manner, we highlight the implementation of different families of fractional-order chaotic oscillators using field-programmable gate arrays (FPGAs). We detail the hardware implementation when solving the mathematical models applying the Grunwald-Letnikov method, and highlight the short-memory principle, which memory length is designed using specialized random-access-memory and read-only-memory blocks. In addition, we show how to reduce hardware resources by reusing blocks that are controlled by an especial architecture that is introduced herein, in order to perform an efficient processing of the data. Finally, using Cyclone IV GX FPGA DE2i-150 from Altera, DAS1612 digital-to-analog converter and fixed-point arithmetic of 32 bits, we provide experimental results that were observed in a Lecroy's oscilloscope showing working frequencies of fractional-order chaotic attractors between 77.59 and 84.9 MHz. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Fractional-order chaotic oscillator field-programmable gate array Grunwald-Letnikov method Fixed-point arithmetic

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A Hardware-Oriented Algorithm for Ultra-High-Speed Object Detection

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IEEE SENSORS JOURNAL 2019年第10期19卷 3818-3831页

作者： Li, Jianquan Liu, Xilong Liu, Fangfang Xu, De Gu, Qingyi Ishii, Idaku Chinese Acad Sci Res Ctr Precis Sensing & Control Inst Automat Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Comp & Control Engn Beijing 101408 Peoples R China Hiroshima Univ Dept Syst Cybernet Robot Lab Hiroshima 7398527 Japan

This paper describes a novel hardware-oriented algorithm that can be implemented on a field-programmable gate array in a high-speed vision platform for detection of multiple objects with clear texture information in images of 512 x 512 pixels at 10000 frames per second (fps) under complex background. The proposed algorithm is specially designed for devices with limited hardware resource for high-frame-rate, high-data-throughput, and high-parallelism processing of video streams with low latency. The proposed algorithm is based on the conventional histograms of oriented gradient (HOC) descriptor and support vector machine classifier algorithms. Considering the trade-off between speed and accuracy, many hardware-based optimization operations were implemented. The data throughput is nearly 29.30 Gbps while the latency for feature extraction is 0.76 us (61 clock period). After hardware-based image processing, the source image and the detected object features can be transferred to a personal computer for recording or post-processing at 10000 fps. Several experiments were done to demonstrate the performance of our proposed algorithm for ultra-high-speed moving object detection with clear texture information in images.

关键词： Hardware implementation high-frame-rate vision field-programmable gate array multi-object detection histograms of oriented gradient support vector machine

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